Tetsuya Asai

A 300 nW, 15 ppm/

A low-power CMOS voltage reference was developed using a 0.35 mum standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745 mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/degC at best and 15 ppm/degC on average, in a range from - 20 to 80degC. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4-3 V, and the power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The power dissipation was 0.3 muW at 80degC. The chip area was 0.05 mm2 . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.

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We describe a majority-logic gate device suitable for use in developing single-electron integrated circuits. The device consists of a capacitor array for input summation and an irreversible single-electron box for threshold operation. It accepts three binary inputs and produces a corresponding output, a complementary majority-logic output, by using the change in its tunneling threshold caused by the input signals; it produces a logical 1 output if two or three of the inputs are logical 0 and a logical 0 output if two or three of the inputs are logical 1. We combined several of these gate devices to form subsystems, a shift register and a full adder, and confirmed their operation by computer simulation. The gate device is simple in structure and powerful in terms of implementing digital functions with a small number of devices. These superior features will enable the device to contribute to the development of single-electron integrated circuits.

C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

This paper proposes a neuromorphic analog CMOS controller for interlimb coordination in quadruped locomotion. Animal locomotion, such as walking, running, swimming, and flying, is based on periodic rhythmic movements. These rhythmic movements are driven by the biological neural network, called the central pattern generator (CPG). In recent years, many researchers have applied CPG to locomotion controllers in robotics. However, most of these have been developed with digital processors and, thus, have several problems, such as high power consumption. In order to overcome such problems, a CPG controller with analog CMOS circuit is proposed. Since the CMOS transistors in the circuit operate in their subthreshold region and under low supply voltage, the controller can reduce power consumption. Moreover, low-cost production and miniaturization of controllers are expected. We have shown through computer simulation, such circuit has the capability to generate several periodic rhythmic patterns and transitions between their patterns promptly.

A majority-logic device using an irreversible single-electron box

We present an analog neuron circuit consisting of a small number of metal-oxide semiconductor (MOS) devices operating in their subthreshold region. The dynamics of the circuit were designed to be equivalent to the well-known Volterra system to facilitate developing the circuit for a particular application. We show that a simple nonlinear transformation of system variables in the Volterra system enables designing a neuron-like oscillator, which can produce sequences in time of identically shaped pulses (spikes) by using current-mode subthreshold MOS circuits. We present experimental results of the fabricated neuron circuits as well as an application in an inhibitory neural network, where the neurons compete with each other in the frequency and time domains.

An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion

Investigation of stochastic resonance in GaAs-based nanowire field-effect transistors (FETs) controlled by Schottky wrap gate and their networks is described. When a weak pulse train is given to the gate of the FET operating in a subthreshold region, the correlation between the input-pulse and source–drain current increases by adding input noise. Enhancement of the correlation is observed in a summing network of the FETs. Measured correlation coefficient of the present system can be larger than that in a linear system in the wide range of noise. An analytical model based on the electron motion over a gate-induced potential barrier quantitatively explains the experimental behaviors.

A subthreshold MOS neuron circuit based on the Volterra system

A low-power CMOS current reference circuit was developed using a 0.35-μm standard CMOS process technology. The circuit consists of MOSFET circuits operating in the subthreshold region and uses no resistors. It compensates for the temperature effect on mobility μ and threshold voltage VTH of MOSFETs and generates a reference current that is insensitive to temperature and supply voltage. Theoretical analyses and experimental results showed that the circuit generates a stable reference current of 100 nA. The temperature coefficient of the current was 520 ppm/°C at best and 600 ppm/°C on average in the range of 0°C-80°C. The line regulation was 0.2%/V in a supply voltage range of 1.8-3 V. The power dissipation was 1 μW, and the chip area was 0.015 mm2. Our circuit would be suitable for use in subthreshold-operated power-aware large-scale integrations.

Stochastic Resonance in Schottky Wrap Gate-controlled GaAs Nanowire Field-Effect Transistors and Their Networks

We developed a CMOS integrated-circuit sensor to monitor the change in quality of perishables that depends on surrounding temperatures. Our sensor makes use of the fact that the temperature dependence of the subthreshold current in MOSFETs is analogous to that of the degradation of perishables. The sensor is attached to perishable goods such as farm and marine products and is distributed from producers to consumers along with the goods. During their distribution process, the sensor measures the surrounding temperatures and emulates the degradation of the goods caused by the temperature. By reading the output of the sensor, consumers can determine whether the goods are fresh or not. Our sensor consists of subthreshold CMOS circuits with a low-power consumption of 10 muW or lower

A 1-

A subthreshold MOS integrated circuit (IC) is designed and fabricated for implementing a competitive neural network of the Lotka-Volterra (LV) type which is derived from conventional membrane dynamics of neurons and is used for the selection of external inputs. The steady-state solutions to the LV equation can be classified into three types, each of which represents qualitatively different selection behavior. Among the solutions, the winners-share-all (WSA) solution in which a certain number of neurons remain activated in steady states is particularly useful owing to robustness in the selection of inputs from a noisy environment. The measured results of the fabricated LV ICs agree well with the theoretical prediction as long as the influence of device mismatches is small. Furthermore, results of extensive circuit simulations prove that the large-scale LV circuit producing the WSA solution does exhibit a reliable selection compared with winner-take-all circuits, in the possible presence of device mismatches.

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A temperature- and supply-independent clock generator has been developed using 0.35-µm CMOS technology. This generator is based on a simple frequency-locked loop technique and can be implemented monolithically without using LC resonant circuits, quartz resonators, and MEMS oscillators. A sample device that is tunable over a wide frequency range of 2–100 MHz was designed and fabricated. It showed a temperature coefficient of 90 ppm/°C, a line regulation of 4%/V, and a power dissipation of 180 µW, at a frequency of 30 MHz. The process sensitivity (σ/μ) was 2.7%. This clock generator can be used as an on-chip reference clock circuit.

600-

A novel silicon retina chip based on the information processing in the vertebrate retina was designed and fabricated. The chip has a novel wiring structure in which all pixels are connected through the channel of MOS transistors, which simplifies a wiring structure compared with conventional resistive networks. The proposed structure minimizes the pixel area and certainly increases a fill factor since each pixel consists of only two photodiodes and three MOS transistors. Experimental results showed that the chip could extracted the edge of input images successfully. Furthermore, it was shown that the chip could operate over a wide range of light intensities by adjusting its spatial resolution.