Kohji Kanamori

A high capacitive-coupling ratio (HiCR) cell for 3 V-only 64 Mbit and future flash memories

A novel contactless cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim tunneling, has been developed for 3 V-only 64 Mbit and future flash memories. A 1.50 /spl mu/m/sup 2/ cell area is obtained by using a 0.4 /spl mu/m technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) advanced rapid thermal process for 7.5-nm thick tunnel oxynitride. The internal voltages used for program and erase are +8 V and +12 V, respectively. The total process-step numbers can be reduced to 85% compared to reported memory cells so far.<<ETX>>

A 3.3 V single-power-supply 64 Mb flash memory with dynamic bit-line latch (DBL) programming scheme

A 3.3 V single-power-supply 64 Mb (4M words x 16b) flash memory with a dynamic bit-line latch (DBL) programming has 50 ns access time and 256 b erase/programming unit-capacity using hierarchical word- and bit-line structures and DBL programming. This memory is fabricated using a 0.4 /spl mu/m-design-rule, double-layer-aluminum, triple-layer-polysilicon, twin-well CMOS technology. To reduce operating voltage, a high-capacitive-coupling ratio (HiCR) cell with high coupling ratio between the control gate and the floating gate is used.<<ETX>>

Impact of mechanical stress on interface trap generation in Flash EEPROMs

We show that the compressive mechanical stress in the channel of a Flash EEPROM cell degrades data retention characteristics through the generation and recovery of traps at the tunnel-oxide/Si substrate interface. To demonstrate this, we measured the mechanical stress and interface trap density in 0.15 /spl mu/m-rule NOR cells using convergent-beam electron diffraction and charge pumping methods. Hydrogen atoms, another possible factor, had less influence than mechanical stress.