Kohei Nakayama

Electrical Properties of Single Crystalline CeO2 High-k Gate Dielectrics Directly Grown on Si (111)

We have grown epitaxial single crystalline CeO2 directly on Si (111) by molecular beam epitaxy. Metal-insulator-semiconductor (MIS) capacitors were fabricated to evaluate electrical properties of CeO2 films. By eliminating an interfacial layer, equivalent oxide thickness (EOT) as small as 0.38 nm was obtained for a CeO2 physical thickness of 5 nm. The dielectric constant (e) was calculated to be e~52, which is two times larger than the value reported for bulk (polycrystalline) CeO2 (e~26). Enhancement of e is probably attributable to the anisotropy of the single crystalline CeO2 and/or the lattice distortion of CeO2 directly grown on Si. A leakage current density of ~ 1 A/cm2 was obtained at an equivalent electrical field of 5 MV/cm for the CeO2 MIS capacitors, which is much smaller than the expected value for SiO2 capacitors with the same EOT. It is revealed that single crystalline CeO2 is promising as an alternative gate dielectric.

Operation of HTS Toggle-Flip-Flop Circuit With Improved Layout Design

Toggle-flip-flop (T-FF) is one of the most important high-Tc superconducting single-flux quantum (HTS SFQ) circuit components and has been designed and fabricated by using YBa2Cu3 O7-delta ramp-edge junction technology. The circuit layout of the T-FF was improved to suppress the junction critical current (Ic) spread in the circuit. Test circuits, which include a T-FF with a single output for evaluating the logic operation and measuring the operating frequency, were fabricated and their operation characteristics were investigated. The T-FF circuit with a single output was successfully operated and finite direct current (dc) supply current margins were obtained at temperatures from 27 to 34 K. Moreover, the maximum operating frequency of the T-FF was estimated to be 360 GHz at 4.2 K and 114 GHz at 41 K. In addition, reduction of dc supply current margins due to thermal noise was also investigated. According to the numerical simulation in which parasitic inductances were taken into account, the narrowest margin in the T-FF circuit wider than plusmn10% was maintained with a bit-error rate (BER) of 10-6 up to 40 K

Fabrication of Ramp-Edge Junctions With High

We have fabricated ramp-edge Josephson junctions using a Cu-poor oxide layer as a precursor of the barrier. La_0.2 - Y_0.9Ba_1.9Cu₃O_x(La-YBCO) and La_0.2 - Yb_0.9Ba_1.9Cu₃O_x (La-YbBCO) were used for the base-electrode and the counter-electrode, respectively. A Cu-poor precursor was deposited on a pattered base-electrode at a substrate temperature (T_s) of approximately 660 degC by a pulsed laser deposition (PLD) method employing deposition conditions different from those for the counter-electrode layer. The fabricated junctions on a La-YBCO ground plane showed resistively and capacitively shunted junction-type current-voltage characteristics. They exhibited the products of the critical current (I_c) and the junction resistance (R_n) higher than 3 mV and excess current ratio less than 30% at 4.2 K. The I_cR_n products were nearly 1.5 times larger than those for junctions with an interface-modified barrier in a temperature range of 4-50 K. The junctions had a barrier region with the thickness of approximately 1 nm and a Cu-poor transition region narrower than that for the latter type of junctions.

I_{\rm c}R_{\rm n}

We have investigated the distribution of critical current density (Jc) for interface-modified ramp-edge Josephson junctions in high-Tc single flux quantum (SFQ) circuits. The 1? spread of Jc in a toggle flip-flop test circuit with a conventional layout is 26.7% and much larger than typical values obtained for junction series-arrays. It is found that the large spread comes from the substantial dependence of Jc on the size of base electrodes, which seems associated with a difference in their surface temperature during deposition of a counter electrode and the formation mechanism of interface-modified junctions. By employing separated base electrodes with similar size in a circuit layout, the Jc spread was drastically reduced to 8.4%, which is almost the same as typical values for junction arrays.

Products by Using Cu-Poor Precursor

Single flux quantum (SFQ) circuit components such as an SFQ-dc converter and a confluence buffer have been fabricated by using an YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// ramp-edge junction technology and their logic operations at temperatures up to near 60 K were investigated. The SFQ-dc converter was correctly operated in a wide temperature range from 4.2 K to 56 K and found to be useful for detecting output signals from other SFQ circuit components at any operating temperatures. The basic function that a signal from either of two input Josephson transmission lines (JTLs) was transmitted to an output JTL was confirmed for the confluence buffer and finite operating margins were obtained at temperatures from 42 K to 61 K. The narrowest margin of dc supply current obtained at temperatures from 55 K to 60 K was /spl plusmn/20% and was consistent with the simulation. Margin reduction due to thermal noise was also evaluated. According to the analytical calculation, the operating margin to keep the bit-error rate less than 10/sup -5/ was as large as /spl plusmn/20% even at 50 K when the value of junction critical-current I/sub c/ was kept near 0.4 mA.

Improvement of Critical Current Density Uniformity for Interface-Modified Josephson Junctions in Single Flux Quantum Circuits

We have proposed narrow-band filter for transmitter of Radar application. A transmitting hybrid filter consists of superconducting resonators and conventional cavity. Novel hybrid filter structured with sandwich in superconducting resonators between two cavities realizes low power concentration in superconducting resonators. Compatibility of the high power handling capability and the sharp skirt feature is possible by this filter. As a result, power handling capability for the hybrid filter was obtained 537 W. Given these features, the transmitting signal with low spurious and the high density carrier frequency assignment for next-generation Radar applications is expected to be realized by applying these filters.

High-temperature operation of oxide SFQ-circuit-elements

Surface treatments have been applied to a multilayer structure in order to improve its surface smoothness and crystallinity for fabricating HTS-SFQ circuits. The surface treatments consist of ion beam etching and annealing in oxygen atmosphere. These surface treatments were applied to a SrSnO/sub 3/ insulating layer on a La-YBCO grandplane as an underlayer for growth of a La-YBCO base layer. From RHEED observation, it was found that a contamination layer or an amorphous layer formed on the SrSnO/sub 3/ surface after the bilayer was exposed to oxygen plasma for removing a photoresist film. The SrSnO/sub 3/ surface structure was observed to be recovered through the ion etching and subsequent annealing procedure. XRD measurement revealed that FWHM of the SrSnO/sub 3/ [200] rocking curve reduced from that of the as-deposited SrSnO/sub 3/ after an annealing at 715/spl deg/C in 120 mTorr oxygen atmosphere, indicating that crystallinity of the SrSnO/sub 3/ layer was also slightly improved. The recovery process for the SrSnO/sub 3/ layer significantly improved the surface roughness Ra and the J/sub c/ at 4.2 K of the La-YBCO base layer.

Narrow-Band Filter for Transmitter of Radar Application

We have developed a low-profile high-sensitivity sub-array module for an active phased array antenna. By using this sub-array module, a low noise receiving antenna can be easily available for wireless applications such as radar systems, communication systems, and so on. In this paper, we describe the new 16 elements S-band multichannel receiving sub-array module using high-temperature superconducting (HTS) filters as a key component for an active phased array antenna. Each receiving channel correspond to an antenna element consists of a HTS filter, a low noise amplifier (LNA), and interface circuits. In the sub-array module, 16 channel circuits are contained within a 200 mm×240 mm×30 mm vacuum chamber and cooled by a small cooler to 77 K. By using HTS filters and the cooler, feed-line loss and internal noise can be substantially reduced. Therefore, high sensitivity for an active phased array antenna can be realized. Additionally, radio wave interferences can be suppressed effectively by sharp frequency selectivity of the HTS filter with high-Q factor.

Fabrication of high-quality multilayer structure for HTS-SFQ circuits using surface treatments

We have developed a high sensitivity receiving sub-array module for an active phased array antenna. By this sub-array module, a low noise receiving antenna can be easily available for wireless applications such as communication systems, radar systems, and so on. In this paper, we describe the 16 elements S-band multichannel receiving sub-array module using high-temperature superconducting (HTS) filters as a key component for an active phased array antenna. Each receiving channel correspond to an antenna element consists of a limiter, a HTS filter, a low noise amplifier (LNA) and interface circuits. In the sub-array module, 16 channel circuits are contained within a 200 mm × 240 mm × 100 mm vacuum chamber and cooled by a common stirling cooler to 77 K. By using HTS filters and the cooler, feed-line loss and internal noise can be substantially reduced. Therefore, high sensitivity for an active phased array antenna can be realized. Additionally, radio wave interferences can be suppressed effectively by sharp frequency selectivity of the HTS filter with high-Q factor.

Low-profile high-sensitivity sub-array module with HTS filters for an active phased array antenna

Abstract The crystal structure, in-plane resistivity, and thermopower for (Pb 2 Cu)Sr 2 Dy x Ce n − x − δ Cu 2 O 2 n +6 (Pb-32 n 2 phase, n =5 or 6) have been studied as a function of Dy content, x , in the fluorite block to ascertain the limit of hole doping. The samples were grown by sequential deposition using the molecular beam epitaxy technique. For n =5, a single phase sample was obtained in the range of 0.9 x x from 1.0 to 1.6, the hole density slightly increased. For the sample with x >1.6, resistivity and thermopower abruptly increased beyond the value for x =1.0, suggesting the electronic state change without changes in crystallinity. The ab-initio electronic structure calculations suggest that the substitution of Ln 3+ for Ce 4+ in the fluorite block has two effects detrimental to conducting properties and superconductivity: (a) creation of vacancy or the hole trap at the oxygen site in the fluorite block, and (b) decrease of the distance between Cu and apical oxygen. These effects may explain the experimental results. They are also considered to be the reasons for the absence of superconductivity in the layered cuprates having a multiple fluorite-type block with n ⩾3.