Osami Horibe

Influence of Counter-Layer Deposition Condition on Critical Current Spread in Interface-Modified Ramp-Edge Junction Arrays

We have fabricated interface-modified ramp-edge junctions and junction arrays with sputtered La-doped YBa2Cu3Oy (La-YBCO) and La-doped YbBa2Cu3Oy (La-YbBCO) by pulsed laser deposition (PLD) as base and counter layers, respectively. The influences of deposition conditions for the La-YbBCO counter layers, in particular the target–substrate distance (Ht–s), on the junction properties and the Ic spread in the junction arrays is investigated. For a relatively short Ht–s of 60 mm, junctions with different edge directions exhibit substantially different Ic values, suggesting that the barrier recrystallization is significantly influenced by the incident angle of ablated atoms on the ramp surface. By employing a longer Ht–s of 80 mm, this influence can be lessened, and 1 σ spreads in Ic at 4.2 K of 7.9 and 9.5% can be obtained for 100- and 1000-junction series arrays, respectively.

Observation of Barrier Recrystallization Process and Properties of Ramp-Edge Josephson Junctions with Interface-Modified Barrier

We have studied the recrystallization process and the microstructure of the interface-modified barrier, and the electrical properties of Josephson junctions with the barrier. Electron cyclotron resonance (ECR) ion bombardment was used for making an amorphous layer at the YBa2Cu3O7� � (YBCO) film surfaces. Then, the samples were annealed to form an interfacemodified barrier from the amorphous. A halo pattern showing the existence of an amorphous was changed to three types of patterns by changing the ECR and annealing conditions. The YBCO surface damaged at an ion acceleration voltage of 700 V showed clear recrystallization to YBCO. The surface damaged at lower voltages showed reflection high energy electron diffraction (RHEED) patterns different from that of YBCO. In these cases, regions with a cubic or pseudo-cubic structures were observed at the interface by transmission electron microscopy (TEM). Ramp-edge Josephson junctions with an interfacemodified barrier have been fabricated. The junction properties strongly depend on the distance between the sample and the laser plume when upper layer YBCO is deposited. The junctions fabricated under optimum conditions exhibited resistively and capacitively shunted junction (RCSJ)-like I–V curves with a typical IcRn product at 4.2 K of 1.0–3.2 mV. We show that the recrystallization of an interface-modified barrier from an amorphous layer strongly depends on the kinetic energy from laser plume plasma as well as the thermal energy from substrate heating, and the Ic values of the junctions strongly depend on the actual bombardment energy of ions incident on the ramp surface. The difference of Ic may be explained in terms of the difference of the barrier microstructure which depends on the ion bombardment energy. [DOI: 10.1143/JJAP.41.1998]

Fabrication and logic operation of oxide SFQ-circuit-components

Basic SFQ circuit components, such as SFQ-dc converter, set-reset flip-flop (RS-FF), confluence buffer and splitter, have been fabricated by the YBa/sub 2/Cu/sub 3/O/sub 7-x/-ramp-edge-junction technology and their logic operations were investigated. Circuit parameters were optimized in order to widen the margins of these oxide SFQ circuit components. The SFQ-dc converter that comprised double SQUIDs connected in series showed the output voltage as much as 0.3 mV at 22 K owing to high I/sub c/R/sub n/ value of the ramp-edge junction. Logic operations of the RS-FF, the confluence buffer and the splitter were correctly performed by using the SFQ-dc converter. Finite operating margins were obtainable for these circuits up to the temperature near 30 K.

Influence of deposition conditions of La-doped YbBa2Cu3Oy upper layers on electrical properties of interface-modified ramp-edge junction

Abstract We have fabricated interface-modified ramp-edge junctions with sputtered La-doped YBa 2 Cu 3 O y (La-YBCO) and La-doped YbBa 2 Cu 3 O y (La-YbBCO) by pulsed laser deposition as base and counter-layers, respectively. The influences of deposition parameters for the La-YbBCO counter-layers on the electrical properties and I c spread of the junctions are investigated. Junctions with resistively and capacitively shunted junction-like I – V characteristics and a typical I c R n of 2–3 mV at 4.2 K can be fabricated in the substrate temperature range of 640–700 °C. By optimizing the deposition parameters including the target–substrate distance, a 1σ spread in I c as small as 8.7% is obtained for 25-junction series array.

Evaluation of fabrication process for interface-modified ramp-edge junctions

Abstract We have examined the parameters in the fabrication process of interface-modified ramp-edge junctions which influence their Ic spread. The distribution of ion-beam energy and the uniformity of ion beam for making an amorphous layer and the base-electrode film quality such as the density of outgrowth or particles and the roughness of the ramp surfaces are important factors determining the Ic spread. We have found another important factor, that is, the recrystallization energy from a laser plume. By adding proper adjustment of the relative location between substrate and the laser plume, Ic spread values of 5.7% and 7.3% have been obtained for arrays of 100 JJ and 1000 JJ, respectively.

Fabrication of interface elements for oxide RSFQ circuits

RSFQ circuit elements were fabricated based on the YBa/sub 2/Cu/sub 3/O/sub 7-x/ ramp-edge junctions and their characteristics were investigated. In particular, two types of interface circuits were designed, fabricated and their amplification functions were evaluated. The interface circuits comprised series array of SQUIDs that shared a common inductor each other. Each SQUID was switched between zero voltage state and voltage state by current injection. Input signal was AC Josephson current for the type-one interface circuit. The input signal was an SFQ for the type-two interface circuit. Both interface circuits could successfully be operated. In particular, an output voltage more than 1 mV was obtained for the type-one interface circuit that comprised the stack of five SQUIDs.

Reflection high energy electron diffraction observation in recrystallization process of surface-modified barrier

Abstract We successfully observed reflection high energy electron diffraction (RHEED) patterns in recrystallization process of surface-modified barrier for Josephson junctions. First, a -axis oriented YBa 2 Cu 3 O 7− δ (YBCO) films were deposited on SrTiO 3 substrates. Electron cyclotron resonance (ECR) ion bombardment was used for making an amorphous layer at the YBCO film surfaces at room temperature. Then, the samples were annealed to form a surface-modified barrier from the amorphous layer. RHEED patterns were observed at several points of this in-situ recrystallization process. RHEED patterns of a typical tri-layered perovskite structure were observed for as-deposited a -axis oriented YBCO films. A halo pattern showing the existence of an amorphous layer was changed to three types of patterns by changing the ECR and annealing conditions. The YBCO surface damaged at the ion acceleration voltage of 700 V showed clear recrystallization to a -axis oriented YBCO after annealing at the temperature of 700°C in 200 mTorr oxygen atmosphere. The surface damaged at lower voltages showed RHEED patterns different from that of a -axis oriented YBCO. In these case, regions with a cubic structure were observed at the interface by TEM.

Evaluation of fabrication process and barrier structure for interface-modified ramp-edge junctions

Abstract For SFQ circuits using high-Tc Josephson junctions, it is very important to reduce the Ic spread of the junctions. We have studied several causes of the Ic spread in interface-modified ramp-edge junctions. First, the relation between the structure and the fabrication process of the barrier has been examined. Reflection high energy electron diffraction pattern observation in the recrystallization process of the interface-modified barrier and transmission electron microscopy observation indicate that several types of barrier structures appear by changing the electron cyclotron resonance ion-bombardment and subsequent annealing conditions. Ion bombardment at a high acceleration voltage of 700 V induces no cubic layer at the interface, while several types of cubic structure can be observed for lower acceleration voltages (300–500 V). Thus, distribution of ion beam energy is one of the important factors determining the Ic spread. We also report the importance of other factors including the uniformity of ion beam for making an amorphous layer, and the base-electrode film quality such as the density of outgrowth or particles and the roughness of the ramp surface. By improving these factors in the junction fabrication process, an Ic spread of 17% has been obtained for an array of 1000JJs with a relatively small average Ic of 0.1 mA, suggesting a possibility of further improvement for junctions with a higher Jc.

Improved Fabrication Process for Monolithic Integrated High-Tc dc Superconducting Quantum Interference Devices

We have developed a new fabrication process for monolithic integrated high-Tc dc superconducting quantum interference devices (SQUIDs) that enables us to prevent a degradation of the junction Tc. In the new process, bicrystal junctions are fabricated simultaneously with a flux transformer by using the top superconducting layer. The junctions in YBa2Cu3O7-x-based SQUIDs fabricated by this process exhibited a Tc of approximately 85 K, indicating no significant degradation. In contrast, conventional monolithic SQUIDs where junctions are fabricated by using the base superconducting layer showed a junction Tc typically below 65 K. A fabricated monolithic dc SQUID magnetometer with a 500 µm square washer, a 23-turn 5-µm-wide input coil, and a pickup loop 6×7 mm2 in outer dimension showed an effective area of 1.2 mm2 and an IcRn of 180 µV at 77 K.

Design and Operation of HTS 1:2 Switch Circuit

A Single flux quantum (SFQ) one-to-two (1:2) switch circuit was designed and fabricated by using YBa2Cu3O7-delta ramp-edge junction technology, and the logic operations were investigated. The circuit parameters were optimized by taking account of an Ic spread and a global Ic shift due to an operation temperature change and insufficient run-to-run reproducibility. In addition, the influence of the parasitic inductance on Ic margins was investigated by simulation. A test circuit including the 1:2 switch circuit was successfully operated at temperatures of 52 K-60 K. Finite dc supply current margins obtained at temperatures of 55 K-60 K were comparable to those determined by the simulation.