Hirokazu Hayashi

Monolithic Pixel Detector in a 0.15 μm SOI Technology

We describe a new pixel detector development project using a 0.15 μm fully-depleted CMOS SOI (silicon-on-insulator) technology. Additional processing steps for creating substrate implants and contacts to form sensor and electrode connections were developed for this SOI process. A diode test element group and several test chips have been fabricated and evaluated. The pixel detectors are successfully operated and first images are taken and sensibility to β-rays is confirmed. Back gate effects on the top circuits are observed and discussed.

ESD protection design using a mixed-mode simulation for advanced devices

In this paper, we propose a new ESD protection design methodology using a mixed-mode ESD simulation that takes account of a coupling effect for both device and circuit. As a result, we can analysis the each protection unit operation and select the optimized protection circuits in prevention of ESD failure on separated power supply units by prediction of the simulation.

SOI pixel developments in a 0.15μm technology

While the SOI (silicon-on-insulator) device concept is very old, commercialization of the technology is relatively new and growing rapidly in high-speed processor and low-power applications. Furthermore, features such as latch-up immunity, radiation hardness and high-temperature operation are very attractive in high energy and space applications. Once high-quality bonded SOI wafers became available in the late 90s, it opened up the possibility to get two different kinds of Si on a single wafer. This makes it possible to realize an ideal pixel detector; pairing a fully-depleted radiation sensor with CMOS circuitry in an industrial technology. In 2005 we started Si pixel R&D with OKI Electric Ind. Co., Ltd. which is the first market supplier of fully-depleted SOI products. We have developed processes for p+/n+ implants to the substrate and for making connections between the implants and circuits in the OKI 0.15mm FD-SOI CMOS process. We have preformed two multi project wafer (MPW) runs using this SOI process. We hosted the second MPW run and invited foreign universities and laboratories to join this MPW run in addition to Japanese universities and laboratories. Features of these SOI devices and experiences with SOI pixel development are presented.

Radiation resistance of SOI pixel devices fabricated with OKI 0.15μm FD-SOI technology

Silicon-on-insulator (SOI) technology is being investigated for monolithic pixel device fabrication. The SOI wafers by UNIBOND allow the silicon resistivity to be optimized separately for the electronics and detector parts. We have fabricated pixel detectors using fully depleted SOI (FD-SOI) technology provided by OKI Semiconductor Co. Ltd. The first pixel devices consisting of 32×32 pixels each with 20 μm square were irradiated with 60Co γ’s up to 0.60 MGy and with 70-MeV protons up to 1.3×1016 1-MeV n eq /cm2. The performance characterization was made on the electronics part and as a general detector from the response to RESET signals and to laser. The electronics operation was affected by radiation-induced charge accumulation in the oxide layers. Detailed evaluation using transistor test structures was separately carried out with covering a wider range of radiation level (0.12 kGy to 5.1 MGy) with 60Co γ’s.

Implementation of ESD Protection in SOI Technology: A Simulation Study

Implementation of ESD protection circuits in SOI technology is well-known to be challenging due to inherent properties of SOI devices. While in comparison to bulk-Si SOI has excellent speed and power consumption features, its current handling capabilities are less impressive. This is due to thin-film current conduction properties and potential heat trapping in the thin film on top of a poor heat conductor (oxide). Design of ESD circuits in SOI is further complicated by the presence of the floating body effect, not adequately considered by conventional circuit simulators. In this work we present results of mixed-mode circuit-device simulation of ESD properties of SOI devices, including film thickness effects, heating during HBM and estimated failure current levels (It2).

Accurate and global model of SOI H gate body-tied MOSFET for circuit simulator

Drain current of SOI H-type body-tied MOSFET can be modulated in gate length or width because of its additional gate region. It causes a serious problem especially in analog circuit design. There is, however, no model including the gate shape effect even in the newest release BSIMSOI [1]. An accurate and global model of SOI H-type body-tied MOSFET in circuit simulation has been proposed for the first time. It is confirmed that the simulation accuracy of the proposed model has greatly improved within 10% RMS error compared to the existing model.

Ion implantation model for channeling through multi-layers

A new implantation model which considers effects of covered layers to channeling effects in substrate is proposed. Physics of energy loss and scattering in covered layers are summarized to a simple expression. The model is easy to implement to any existing process simulators, and accuracy is drastically improved not only for advanced devices but also for legacy devices.

Engineering systematic yield of fully-depleted SOI MOSFET

We propose a new and effective SOI yield engineering methodology by sophisticated usage of 2D simulations. It is revealed by the methodology that, applying a limitation to threshold voltage yield and considering varied SOI layer thickness, the maximum current becomes substantially low. This trade-off relationship is balanced to obtain high maximum current and moderate source-drain breakdown voltage in acceptable turn around time.

Optimization of program and erase characteristics of two bit flash memory P-channel cell structure using TCAD

This paper presents the optimization of the two bit flash memory P-channel cell structure using efficient 2D write and erase model. Our proposed cell structure stores charge at either Source and/or Drain sides of the gate in an SiN film and is based on method of programming by DAHE and erasing by FN tunneling. It is found that expansion of cell window and the improvement of erase characteristic depend on the optimization of the gate-film overlap under gate of the SiN film.

Efficient and universal method to design multiple field limiting rings for power devices

For the first time, an efficient and universal method to design multiple field limiting rings (FLR) structure, which applicable to power devices with thin drift layer is proposed. Avalanche breakdown simulations of simplified structures are performed in each three area; the near main junction area, the outmost area, and the other. From simulation results, optimal spacing between each neighboring FLR is efficiently extracted. Phenomena related breakdown voltage determination in each area are also clarified. We demonstrate that the edge termination structures designed along our guidelines succeed to obtain the target blocking voltage in different 600 V class processes.