Koichi Matsunaga

Comparison of directed self-assembly integrations

Directed Self-Assembly (DSA) is gaining momentum as a means for extending optical lithography past its current limits. There are many forms of the technology, and it can be used for creating both line/space and hole patterns.1-3 As with any new technology, adoption of DSA faces several key challenges. These include creation of a new materials infrastructure, fabrication of new processing hardware, and the development of implementable integrations. Above all else, determining the lowest possible defect density remains the industrys most critical concern. Over the past year, our team, working at IMEC, has explored various integrations for making 12-14nm half-pitch line/space arrays. Both grapho- and chemo-epitaxy implementations have been investigated in order to discern which offers the best path to high volume manufacturing. This paper will discuss the manufacturing readiness of the various implementations by comparing the process margin for different DSA processing steps and defect density for the entirety of the flow. As part of this work, we will describe our method for using programmed defectivity on reticle to elucidate the mechanisms that drive self-assembly defectivity on wafer.

EUV patterning successes and frontiers

The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.

Latest cluster performance for EUV lithography

Previously, fundamental evaluations of the Extreme Ultra Violet (EUV) lithography process have been conducted using the CLEAN TRACK ACT™ 12 coater/developer with the ASML EUV Alpha Demo Tool (ADT) at imec. In that work, we confirmed the basic process sensitivities for the critical dimension (CD) and defectivity with EUV resists. Ultimate resolution improvements were examined with TBAH and FIRM™ Extreme. Moving forward with this work, the latest inline cluster is evaluated using the ASML NXE:3100 pre-production EUV scanner and the CLEAN TRACK™ LITHIUS Pro™ -EUV coater/developer. The imec standard EUV baseline process has been evaluated for manufacturability of CD uniformity control based on half pitch (HP) 27nm and ultimate resolution studies focusing on HP 22nm. With regards to the progress of the improvement for EUV processing, we confirmed the effectiveness of several novel concepts: FIRM™ Extreme10 showed increase in ultimate resolution and improvement in line width roughness (LWR) and process window; Tokyo Electron LTD. (TEL) smoothing process for roughness reduction showed 17% improvement for line and space (L/S) patterns; and finally the new dispense method reduced patterned wafer defectivity by over 50%.

Driving down defect density in composite EUV patterning film stacks

Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates for enabling the next generation devices, for 7nm node and beyond. As the technology matures, further improvement is required in the area of blanket film defectivity, pattern defectivity, CD uniformity, and LWR/LER. As EUV pitch scaling approaches sub 20 nm, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse and eliminate film related defect. IBM Corporation and Tokyo Electron Limited (TELTM) are continuously collaborating to develop manufacturing quality processes for EUVL. In this paper, we review key defectivity learning required to enable 7nm node and beyond technology. We will describe ongoing progress in addressing these challenges through track-based processes (coating, developer, baking), highlighting the limitations of common defect detection strategies and outlining methodologies necessary for accurate characterization and mitigation of blanket defectivity in EUV patterning stacks. We will further discuss defects related to pattern collapse and thinning of underlayer films.

Track processing optimizations for different EUV resist platforms: preparing for a NXE:3300 baseline process

To make sure a baseline process will be ready for the evaluation of the NXE:3300, imec evaluates promising new EUV resist materials with regards to imaging, process window and line width roughness (LWR) performance. From those screening evaluations, highest performing materials meeting dose sensitivity requirements are selected to be installed on the coat/develop track. This work details the process optimization results of the different selected resist platforms with regards to full wafer processing. Evaluations are executed on the ASML NXE:3100 equipped with a laser-assisted discharge produced plasma source from XTREME technologies, and interfaced to a TEL CLEAN TRACKTM LITHIUS ProTM -EUV.

EUV patterning improvement toward high-volume manufacturing

Extreme ultraviolet lithography (EUVL) technology is a promising candidate for a semiconductor process for 18nm half pitch and beyond. So far, the studies of EUV for manufacturability have been focused on particular aspects. It still requires fine resolution, uniform and smooth patterns, and low defectivity, not only after lithography but also after the etch process. Tokyo Electron Limited and imec are continuously collaborating to improve manufacturing quality of the process of record (POR) on a CLEAN TRACKTM LITHIUS ProTMZ-EUV. This next generation coating/developing system has been upgraded with defectivity reduction enhancements which are applied along with TELTM best known methods. We have evaluated process defectivity post lithography and post etch. Apart from defectivity, FIRMTM rinse material and application compatibility with sub 18nm patterning is improved to prevent line pattern collapse and increase process window on next generation resist materials. This paper reports on the progress of defectivity and patterning performance optimization towards the NXE:3300 POR.

Manufacturability improvements in EUV resist processing toward NXE:3300 processing

As the design rule of semiconductor process gets finer, extreme ultraviolet lithography (EUVL) technology is aggressively studied as a process for 22nm half pitch and beyond. At present, the studies for EUV focus on manufacturability. It requires fine resolution, uniform, smooth patterns and low defectivity, not only after lithography but also after the etch process. In the first half of 2013, a CLEAN TRACKTM LITHIUS ProTMZ-EUV was installed at imec for POR development in preparation of the ASML NXE:3300. This next generation coating/developing system is equipped with state of the art defect reduction technology. This tool with advanced functions can achieve low defect levels. This paper reports on the progress towards manufacturing defectivity levels and latest optimizations towards the NXE:3300 POR for both lines/spaces and contact holes at imec.

EUV process establishment through litho and etch for N7 node

Extreme ultraviolet lithography (EUVL) technology is steadily reaching high volume manufacturing for 16nm half pitch node and beyond. However, some challenges, for example scanner availability and resist performance (resolution, CD uniformity (CDU), LWR, etch behavior and so on) are remaining. Advance EUV patterning on the ASML NXE:3300/ CLEAN TRACK LITHIUS Pro Z- EUV litho cluster is launched at imec, allowing for finer pitch patterns for L/S and CH. Tokyo Electron Ltd. and imec are continuously collabo rating to develop manufacturing quality POR processes for NXE:3300. TEL’s technologies to enhance CDU, defectivity and LWR/LER can improve patterning performance. The patterning is characterized and optimized in both litho and etch for a more complete understanding of the final patterning performance. This paper reports on post-litho CDU improvement by litho process optimization and also post-etch LWR reduction by litho and etch process optimization.

Metal containing material processing on coater/developer system

Challenges of processing metal containing materials need to be addressed in order apply this technology to Behavior of metal containing materials on coater/developer processing including coating process, developer process and tool metal contamination is studied using CLEAN TRACKTM LITHIUS ProTM Z (Tokyo Electron Limited). Through this work, coating uniformity and coating film defectivity were studied. Metal containing material performance was comparable to conventional materials. Especially, new dispense system (NDS) demonstrated up to 80% reduction in coating defect for metal containing materials. As for processed wafer metal contamination, coated wafer metal contamination achieved less than 1.0E10 atoms/cm2 with 3 materials. After develop metal contamination also achieved less than 1.0E10 atoms/cm2 with 2 materials. Furthermore, through the metal defect study, metal residues and metal contamination were reduced by developer rinse optimization.

Coater/developer process integration of metal-oxide based photoresist

Inpria is pioneering a novel approach to EUV photoresist. Directly patternable metal oxide thin films have shown resolution better than 10nm half-pitch, with robust etch resistance, and efficient use of photons through high EUV absorbance. Inpria’s Gen2 photoresists are cast from commonly used organic coating solvents and are developed in typical negative tone develop (NTD) organic solvents. This renders them compatible with CLEAN TRACK LITHIUS Pro-EUV coater/developer system (Tokyo Electron Limited; TEL) and solvent drains. The presence of metal in the photoresist demands additional scrutiny and process development to minimize contamination risks to other tools and wafers. In this paper, we review progress in developing coat processes that reduce metal contamination levels below typical industry levels. We demonstrate minimization of trace metals contamination from wafer-to-coater/developer, and wafer-to-wafer from the spin coat process. This will also include results from surface analyses of frontside edge exclusion and backside of wafer using best-known analytical methods. In addition, we discuss results of coat uniformity and defectivity optimization. Wet clean compatibility and dry etch rate by using conventional Si-ARC/OPL etching recipe will also be presented. In conjunction with this work, we identify potential contamination pathways and means for managing contamination risk. We furthermore review equipment compatibility issues for using Inpria’s metal oxide photoresists.