Koichi Ohto

Tradeoff Characteristics Between Resistivity and Reliability for Scaled-Down Cu-Based Interconnects

We investigated tradeoff characteristics between resistivity and reliability for scaled-down Cu-based interconnects. A unique resistivity-measurement technique is proposed to detect influences due to impurity doping. Using this technique, we investigated the impacts of the impurity doping on three types of copper interconnects - cobalt-tungsten-phosphorous (CoWP) metal-cap interconnects, plasma-enhanced chemical-vapor-deposition self-aligned barrier interconnects, and CuAl alloy interconnects - and clarified the tradeoffs between the resistivity and the reliability. We found that the metal-cap interconnect shows not only high reliability but also outstanding efficiency with regard to the suppression of resistance increase due to impurity doping.

A half-micron pitch Cu interconnection technology

Half-micron pitch Cu interconnections have been achieved by self-aligned plug (SAP), MOCVD-TiN barrier layer (MBL), and alumina capped oxidation-free structure (ACOS). Low resistance 0.12 /spl mu/m Cu interconnections whose effective resistivity is 1.9 /spl mu//spl Omega/cm have been obtained. Improved thermal stability up to 600/spl deg/C has been achieved for quarter-micron Cu contacts. Cu oxidation has been suppressed without increasing resistance by using a trimethylaluminum (TMA) treatment.

A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 μm complementary metal oxide semiconductor generation

A robust embedded ladder-oxide (k=2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 µm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 µm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.

A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 /spl mu/m CMOS generation

A robust embedded ladder-oxide (k=2.9)/Cu multilevel interconnect is demonstrated for the 0.13 /spl mu/m CMOS generation. A stable ladder-oxide IMD is integrated into the Cu metallization with minimum wiring pitch of 0.34 /spl mu/m, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with SiO/sub 2/ IMD. The stress-migration lifetime of vias on wide metals for S/D Cu-plug structure is much longer than for dual damascene (D/D). The reliability test results such as those for electromigration (EM), Cu interconnect TDDB, and pressure cooker test (PCT) are quite acceptable. Moreover, high flexibility in thermal design and packaging is obtained.

Quarter-Micron Interconnection Technologies for 256-Mbit Dynamic Random Access Memories

Quarter-micron interconnection technologies for 256-Mbit dynamic random access memories (DRAMs) are reviewed. Since the density of memory capacity is increased, both decreasing feature size and increasing sophistication of cell structures are required, resulting in three-dimensional structures. This trend leads us to the introduction of new interconnection technologies which have good coverage, low resistivity and high reliability, because the three-dimensional device structure requires high aspect-ratio contact hole plugs and narrow-pitch metal lines on different surface levels. The state of the art and current problems are discussed for quarter-micron contact-hole filling and quarter-micron interconnection lines.

Surface Control of Bottom Electrode in Ultra-Thin SiN Metal–Insulator–Metal Decoupling Capacitors for High Speed Processors

Highly reliable metal–insulator–metal (MIM) capacitor with ultra-thin SiN dielectrics is developed on the surface-controlled bottom electrode in nanometer-scales. Coverage of the TiN bottom electrode with a Ta thin layer achieves smooth surface. In addition, this electrode structure exhibits excellent etching controllability even for the MIM with the ultra-thin SiN dielectrics. The smooth surface of the Ta/TiN stacked electrode improves the dielectric characteristics such as leakage, breakdown and time-dependent dielectric breakdown (TDDB) reliability in the MIM capacitors, integrated into Cu dual-damascene interconnects (DDIs). As a result, the SiN-MIM with the Ta/TiN bottom electrode achieves high capacitance of 7 fF/µm2 as well as high reliabilities, which are 20% higher breakdown field and 6000 times longer TDDB lifetime than that without Ta-insertion. These values guarantee the high performance operation for more than 10 years under the environment at 85 °C.