Tatsuya Usami

Mechanical properties of SiCOH film related to CPI and High Load Indentation test of real Cu/Low-k structure with bumps

Relation between mechanical properties of SiCOH film and white bump failures has been investigated. Among these mechanical properties, the fracture toughness of SiCOH film was related to the white bump failures. In addition, to simplify the complex Chip Package Interaction (CPI) tests, we proposed High Load Indentation (HiLI) test as a novel measurement of toughness for a real structure of multilayer Cu/Low-k interconnects with Pb-free bump. We found that the critical load by HiLI test is related to white bump failure.

Impact of low-k moisture absorption during queue-time on Cu-alloy/low-k reliability and its suppression

The moisture absorption impacts on electromigration (EM) and time-dependent dielectric breakdown (TDDB) were investigated in Cu alloy/low-k interconnects. A long queue time (Q-time) has a serious impact on kinetics of both EM and TDDB characteristics. The moisture absorption causes the loss of alloy effects on EM lifetime improvements. The ultra-thin SiN (UT-SiN) remarkably suppresses the moisture absorption impacts due to Q-time. It also improves kinetics degradations of EM and TDDB that depend on the moisture absorption to low-k.

Early screening method of chip-package interaction for multi-layer Cu/low-k structure using high load indentation test

We have developed High Load Indentation (HiLI) test as a novel early screening method of Chip-Package Interaction (CPI) for multi-layer Cu/Low-k interconnects structure with bumps. In this study, by using HiLI test, we evaluated a lower fracture toughness SiCOH (Low-k), a thicker under bump metallization (UBM) and a plasma-damaged polyimide (PI) around these bumps, whose white bump failures relatively tend to occur compared to the standard structure. We found that both these in-situ load profiles and observations after the test corresponded with these white bump failures. In addition, we compared between a polished bump structure and an un-polished bump one by the test.

Control of plasma polymerization reaction for the 2 nd generation molecular_pore_stack (MPS) SiOCH film with high deposition rate

To reducing BEOL fabrication cost for 28/20nm-nodes, high-speed process of the low-k deposition is needed under limited equipment investment. By using a standard plasma-CVD equipment with no post-cure process, we have developed high speed deposition technique for a molecular_pore_stack (MPS) SiOCH film from single precursor, which has a hexagonal-silica-ring with hydrocarbon side-chains. Here, the plasma polymerization reaction of the precursors was enhanced simply by controlling the RF power and the gas chemistry with additive gas, which was dissociated itself to increase active charge flux in the plasma. The deposition rate was doubled while keeping the film properties unchanged with the sub-nanometer-size porous structure. No change in the RC performance of the Cu interconnect was observed by using the new MPS film with the high deposition rate. The mechanical properties also were preserved to keep chip-packaging-interaction tolerance.

Highly reliable Enhanced Nitride Interface (ENI) process of barrier Low-k using absorption-free Ultra-Thin SiN (UT-SiN)

A highly reliable Enhanced Nitride Interface (ENI) process of barrier Low-k using an Ultra-Thin SiN (UT-SiN) has been developed for 40-nm node and beyond. The UT-SiN (3nm) has a good thickness uniformity and a good stability against absorption. By using this technique, a lower effective k and good via yields were obtained. In addition, 5x via electro-migration (EM) improvement, 50x TDDB and no SIV failure by 1000h were obtained in comparison to the conventional SiCN bi-layer process. And the ENI was analyzed by XPS and TOF-SIMS. According to these analyses, the mechanism for performance enhancement is proposed.