Koichiro Furuta

A GHz MOS adaptive pipeline technique using MOS current-mode logic

This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-/spl mu/m MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits.

A 30-ns 256-Mb DRAM with a multidivided array structure

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25- mu m CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 mu m/sup 2/. Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm/sup 2/. >

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking

A 1.5-W single-chip MPEG-2 MP@ML real-time video encoder large scale integrated circuit (LSI) has been developed. To form an MPEG-2 encoder system, we employ two 16-Mb synchronous DRAMs, a microprocessor unit (MPU), and an audio encoder LSI. Owing to a two-step hierarchical search scheme and a novel adaptive search window scheme, the search range of motion estimation is -48/+47 horizontal and -96/+15.5 vertical, and the pseudo search range, which is the size when the location of the search window is adaptively shifted, is -96/+95 horizontal and -32/+31.5 vertical. We have also developed low-power clocking techniques, i.e., demand-clock controller, local-clock controller, and low-power flip-flops, which can eliminate waste of power in clocking. We have successfully fabricated these new designs as a low-power single-chip MPEG-2 encoder LSI. The operating frequency except for a synchronous DRAM interface unit and a video in/out unit is 54 MHz. The supply voltage to the first and second search engines in a motion estimation unit can be successfully lowered to 2.5 V and the others are 3.3 V. Into a 12.45/spl times/12.45 mm/sup 2/ chip with 0.35-/spl mu/m CMOS and triple-metal layer technology are integrated 3.1 M transistors.

A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture

Reconfigurable logic LSIs, such as FPGAs, have been perceived as devices for prototyping and emulation. As the size and speed of FPGAs rapidly increase, however, they have begun to be used in /spl mu/P-based systems as reconfigurable accelerators. The idea is to achieve both hardware efficiency and software programmability by dynamically reconfiguring FPGAs. This idea, reconfigurable computing, provides an attractive solution especially for media/network-centric applications. Various types of reconfiguration scenarios in such applications, however, require logic LSIs to significantly enhance reconfigurability in three respects: (1) agility-reconfiguration may need to take place in very short intervals, say within a hundred /spl mu/P instructions; (2) controllability-reconfiguration may be controlled from an external /spl mu/P or by itself; (3) flexibility-reconfiguration target may be arbitrarily positioned and irregularly shaped. The dynamically reconfigurable logic engine (DRLE) prototype described meets this challenge.

A 5 ns 1 Mb ECL BiCMOS SRAM

A 1 M-word*1-b emitter-coupled-logic (ECL) SRAM in 0.8- mu m BiCMOS technology that achieves 5-ns access time using (1) wired-OR predecoders, (2) ECL CMOS level converters with partial address decoding, and (3) sensing with small differential voltage swing on long read bus lines is described. The memory cell array is divided into two 512 K-cell subarrays. Each subarray consists of 16 32-kb arrays, each of which is organized into 256 rows and 128 columns. An X-decoder is located between a pair of 32-kb arrays. Address input signals are received by an ECL address buffer. The first circuit for address decoding is a wired-OR predecoder, which does the predecoding and predecoded signal line driving. Predecoded address signals with about 1.2-V voltage swing drive 16.5-mm predecoded lines between two 512-kb subarrays and are received by partial-decoding level converters at corresponding 32-kb arrays.<<ETX>>

A 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core

This paper describes a 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core which is composed of a 2-mW 16-b multiplier-accumulator and a 1.5-mW 8-kb SRAM. High-speed operation with a supply of less than 1 V has been achieved by developing 0.25-/spl mu/m CMOS technology, reducing threshold voltage to 0.3 V, developing tristate inverter 3-2/4-2 adders for the multiplier, realizing small bit-line swing operation for the SRAM, and so on. The adder circuits operate faster than conventional adders at low supply voltages. In addition, short-circuit current and area for diffusion contact are reduced. Small bit-line swing operation has been realized by using a device-deviation immune sense amplifier. Leakage current during sleep mode was reduced by the use of high threshold voltage MOSFETs.

Elastic-Vt CMOS circuits for multiple on-chip power control

The elastic-Vt CMOS (EVTCMOS) circuit design controls MOS transistor source (not substrate) voltages, so fabrication requires no special steps. The post-fabrication threshold voltages can be switched back and forth between high Vt (sleep mode) and low Vt (active mode), and can be also controlled as a means of reducing the sensitivity to device-parameter deviations and operating-environment variations. This results in reduction of switching time between sleep and active modes, and in reduced static power consumption in sleep mode.

Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI

We have used DES and Reed-Solomon applications to evaluate a dynamically reconfigurable logic engine (DRLE) LSI and have spatially mapped and temporally partitioned these applications into multiple contexts of a DRLE LSI. The evaluation shows that the DRLE improved by more than an order of magnitude over the conventional low-power /spl mu/P in both performance and energy consumption. We believe DRLEs scalability against various size applications, which is achieved by dynamic reconfiguration among multiple contexts, will be invaluable for on-chip programmable IP cores in system LSIs.

A virtual hardware system on a dynamically reconfigurable logic device

WASMII is virtual hardware using a multi-context reconfigurable device with a data driven control. Since implementation of WASMII was infeasible due to the unavailability of such a device, the system has been only evaluated using an emulator so far. However, the first reconfigurable multi-context device called DRL has been developed by NEC. Making the use of its flexible reconfigurability, we have implemented a mechanism of WASMII on DRL.

A 0.18 /spl mu/m CMOS hot-standby phase-locked loop using a noise-immune adaptive-gain voltage-controlled oscillator

This PLL features a hot-standby PLL (HSPLL) architecture and noise-immune circuit techniques. With this architecture, both fast lock time and low jitter are achieved by the system transfer function being changed; it is unnecessary to vary the values of system parameters in an attempt to reduce lock time. The HSPLL uses a reconfigurable delay line (RDL) that, depending upon the state of its switch circuit (SC), can operate either as a voltage-controlled delay line (VCDL) or a voltage-controlled oscillator (VCO). When the RDL is operating as a VCDL (i.e. when the total circuit is a VCDL-PLL, a first-order system), lock time is fast and jitter is low, but it is difficult to generate a frequency-multiplied signal. This makes the VCDL-PLL configuration appropriate for the unlocked state. Then, at the instant that the HSPLL changes from the unlocked state to the locked, the condition of the SC is changed to create a VCO-PLL, a second-order system in which it is easy to generate a frequency-multiplied signal but difficult to achieve fast lock time (i.e. a situation well-suited to a locked state). This HSPLL architecture allows use of the respective advantages of both VCDL- and VCO-PLLs without having to suffer from their various disadvantages. The HSPLL is implemented in 0.18 /spl mu/m CMOS and two-layer metal technology. 2010 transistors are integrated into a 480/spl times/450 /spl mu/m/sup 2/ die area. The supply voltage is 1.0 V, the power dissipation is about 2 mW, the input signal frequency is 50 MHz, and the output signal frequency is 200 MHz.