Masakazu Yamashina

A GHz MOS adaptive pipeline technique using MOS current-mode logic

This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-/spl mu/m MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits.

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking

A 1.5-W single-chip MPEG-2 MP@ML real-time video encoder large scale integrated circuit (LSI) has been developed. To form an MPEG-2 encoder system, we employ two 16-Mb synchronous DRAMs, a microprocessor unit (MPU), and an audio encoder LSI. Owing to a two-step hierarchical search scheme and a novel adaptive search window scheme, the search range of motion estimation is -48/+47 horizontal and -96/+15.5 vertical, and the pseudo search range, which is the size when the location of the search window is adaptively shifted, is -96/+95 horizontal and -32/+31.5 vertical. We have also developed low-power clocking techniques, i.e., demand-clock controller, local-clock controller, and low-power flip-flops, which can eliminate waste of power in clocking. We have successfully fabricated these new designs as a low-power single-chip MPEG-2 encoder LSI. The operating frequency except for a synchronous DRAM interface unit and a video in/out unit is 54 MHz. The supply voltage to the first and second search engines in a motion estimation unit can be successfully lowered to 2.5 V and the others are 3.3 V. Into a 12.45/spl times/12.45 mm/sup 2/ chip with 0.35-/spl mu/m CMOS and triple-metal layer technology are integrated 3.1 M transistors.

A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture

Reconfigurable logic LSIs, such as FPGAs, have been perceived as devices for prototyping and emulation. As the size and speed of FPGAs rapidly increase, however, they have begun to be used in /spl mu/P-based systems as reconfigurable accelerators. The idea is to achieve both hardware efficiency and software programmability by dynamically reconfiguring FPGAs. This idea, reconfigurable computing, provides an attractive solution especially for media/network-centric applications. Various types of reconfiguration scenarios in such applications, however, require logic LSIs to significantly enhance reconfigurability in three respects: (1) agility-reconfiguration may need to take place in very short intervals, say within a hundred /spl mu/P instructions; (2) controllability-reconfiguration may be controlled from an external /spl mu/P or by itself; (3) flexibility-reconfiguration target may be arbitrarily positioned and irregularly shaped. The dynamically reconfigurable logic engine (DRLE) prototype described meets this challenge.

A 3.84 GIPS integrated memory array processor LSI with 64 processing elements and 2 Mb SRAM

An integrated memory array processor (IMAP) LSI has peak performance of 3.84 GIPS and is suitable for high-speed, low-level image processing (LIP). Keys to performance are: integration of 64 simple processing elements (PEs) and 2 Mb SRAM with 128 b I/O, and single-instruction stream multiple-data stream (SIMD) parallel processing by use of 1.28 GB/s on-chip processor-memory bandwidth. A large number of active sense amplifiers ordinarily used in a wide memory bandwidth creates the problem of large power consumption. The number of active sense amplifiers here is reduced by a factor of 4 by accessing half of each word at a time, but accessing it at twice the speed of the PE clock. This keeps power consumption low. Each memory block can perform indexed addressing within its pages. This capability contributes to IMAP flexibility and efficiency in LIP. To raise yield, the architecture employs 4-way block replacement redundancy. IMAP is fabricated in 0.55 /spl mu/m BiCMOS 2-layer metal process technology. >

Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI

This paper presents a new circuit scheme called a transient sensitive accelerator (TSA) circuit for highly resistive interconnects. The TSA can reduce both delay time and crosstalk voltage. Using the TSA with an interconnect length of 30 mm reduces delay time and crosstalk voltage by 29% and 20%, respectively. A further advantage is that the TSA operates in self-time and thus can be applied to bidirectional signal communication.

A 1 GHz portable digital delay-locked loop with infinite phase capture ranges

Delay-locked loops (DLLs) are widely used to align signal phases in many high-speed microprocessors and memories. Phase-locked loops (PLLs) are also used but their jitter is larger than that of DLLs, because DLLs have no jitter accumulation. However, conventional DLLs have design problems. One is that their phase capture ranges are limited, and another is that a special reset sequence is required. Dual DLL architectures are developed to overcome these problems. In these architectures, the latency from the input to the output, however, is lengthened to attain high resolution, because these architectures require a number of multiplexers between the DLL input and output ports. As a result, supply-noise induced jitter increases. To reduce the jitter, a portable digital DLL uses the following techniques: (1) a master-slave architecture, which achieves infinite phase capture ranges and eliminates the special reset requirement, (2) a wave synchronous latch circuit, which maintains high resolution, and (3) a dynamic phase detector, which improves phase comparison sensitivity.

250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI

A 250-MHz, 16-b, fixed-point, super-high-speed video signal processor (S-VSP) ULSI has been developed for constructing a video teleconferencing system. Two major technologies have been developed. One is a high-speed large-capacity on-chip memory architecture that achieves both 250-MHz internal signal processing and 13.5-MHz input and output buffering. The other is a circuit technology that achieves 250-MHz operations with a convolver/multiplier, an arithmetic logic unit (ALU), an accumulator, and various kinds of static RAMs (SRAMs). A phase-locked loop (PLL) is also integrated to generate a 250-MHz internal clock. The S-VSP ULSI, which was fabricated with 0.8- mu m BiCMOS and triple-level-metallization technology, has a 15.5-mm*13.0-mm area and contains about 1.13 million transistors. It consumes 7 W at 250-MHz internal clock frequency with a single 5-V power supply. >

A 1 GIPS 1 W single-chip tightly-coupled four-way multiprocessor with architecture support for multiple control flow execution

A 125 MHz 1 GIPS at 1.3 V 1 W microprocessor with single-chip tightly-coupled multiprocessor architecture and low-voltage circuits is targeted to high-performance and low-power embedded systems, especially smart information terminals. This paper shows an entire chip diagram integrating four tightly-coupled processors. Each processing element (PE) is in-order two-way issue superscalar with two ALU pipelines. A power-management unit (PMU) cuts off the leakage current of each power-control domain independently using dedicated power switches.

A 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core

This paper describes a 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core which is composed of a 2-mW 16-b multiplier-accumulator and a 1.5-mW 8-kb SRAM. High-speed operation with a supply of less than 1 V has been achieved by developing 0.25-/spl mu/m CMOS technology, reducing threshold voltage to 0.3 V, developing tristate inverter 3-2/4-2 adders for the multiplier, realizing small bit-line swing operation for the SRAM, and so on. The adder circuits operate faster than conventional adders at low supply voltages. In addition, short-circuit current and area for diffusion contact are reduced. Small bit-line swing operation has been realized by using a device-deviation immune sense amplifier. Leakage current during sleep mode was reduced by the use of high threshold voltage MOSFETs.

A single-chip multiprocessor for smart terminals

Merlot, the first MP98 architecture prototype, promises 1-GIPS performance at 1 watt for 1.3-V operations in support of smart 21st-century information terminals.