Hiroyuki Igura

A GHz MOS adaptive pipeline technique using MOS current-mode logic

This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-/spl mu/m MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits.

A 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core

This paper describes a 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core which is composed of a 2-mW 16-b multiplier-accumulator and a 1.5-mW 8-kb SRAM. High-speed operation with a supply of less than 1 V has been achieved by developing 0.25-/spl mu/m CMOS technology, reducing threshold voltage to 0.3 V, developing tristate inverter 3-2/4-2 adders for the multiplier, realizing small bit-line swing operation for the SRAM, and so on. The adder circuits operate faster than conventional adders at low supply voltages. In addition, short-circuit current and area for diffusion contact are reduced. Small bit-line swing operation has been realized by using a device-deviation immune sense amplifier. Leakage current during sleep mode was reduced by the use of high threshold voltage MOSFETs.

An autonomous reconfigurable cell array for fault-tolerant LSIs

The integration density achieved by the sub-0.l/spl mu/m ULSI causes a serious reliability problem. Redundancy is essentially the solution to the problem, but it is difficult to introduce redundancy to logic LSIs because of their functional complexity compared to memory LSIs. To overcome this difficulty, the autonomous reconfigurable cell array (ARCA) takes advantage ofthe redundancy, regularity, and programmability of reconfigurable logic circuits. It self-detects faults in real-time and automatically recovers while remaining on-line. Fault-tolerant LSIs can be obtained simply by mapping an objective circuit onto an ARCA in the same way as in conventional programmable LSIs.

A 500 MHz, 32 bit, 0.4 /spl mu/m CMOS RISC processor

A 500 MHz, 32 bit RISC microprocessor has been experimentally developed using an 8-stage pipelined architecture and high-speed circuits, including a 500 MHz 1 kilobyte double-stage pipelined cache, a 1.8 ns register file, a double-stage binary look-ahead carry (BLC) adder circuit, and a 500 MHz phase locked loop (PLL) frequency multiplier. Newly developed circuit-integrating techniques include a stacked power-line structure, which serves as a noise shield and also provides low bounce, a low voltage-swing interface circuit with on-chip adjustable termination resistors, a small-skew clock distribution method, and a clock synchronization circuit which provides small-skew clock among LSI chips. About 200000 transistors are integrated into a 7.90 mm/spl times/8.84 mm die area with 0.4 /spl mu/m CMOS fabrication technology. Power dissipation is 6 W at a 500 MHz operation and 3.3 V supply voltage. >

An 800 MOPS 110 mW 1.5 V parallel DSP for mobile multimedia processing

The central signal-processing unit for a portable multimedia terminal in the coming wide-band wireless communication age should meet the following three requirements: (1) high-performance for processing video-class wide-band digital signals, (2) low-power for extended battery life, (3) programmability to cope with applications with a small chip count. Conventional DSPs lack the high-performance, while emerging media processors consume too much power. This DSP exploits task-level, coarse-grained parallelism inherent in multimedia applications. This chip achieves performance in a power-efficient manner, while maintaining the programmability of conventional DSPs.

A 1.5% jitter PLL clock generation system for a 500-MHz RISC processor

We have developed a clock generation system for RISC processors. The system consists of two parts of a PLL, a frequency multiplier, and a phase aligner. The multiplier can multiply the input clock frequency by 2, 4, and 8, and can accomplish a wide frequency range of output clocks, from 60 MHz to 660 MHz. Jitter is reduced to 1.5% of the output clock period by separating the clock generation system into a frequency multiplier and a phase aligner, and by developing a new differential loop filter with high sensitivity phase detection. The phase aligner reduces clock skew between the processor and peripheral LSIs. The system is fabricated with 0.4-/spl mu/m CMOS triple-layer Al process technology and operated at 3.3 V.<<ETX>>

A low-power W-CDMA demodulator using specially-designed micro-DSPs

This paper presents the architecture of a demodulator developed for W-CDMA digital baseband processing. The demodulator features micro-DSPs specially designed for it and a variety of power-lowering and area-saving techniques such as detailed clock control, reduction of unnecessary signal transition and data compression. These features give the demodulator much lower power consumption and smaller size than a conventional one.

A 400 MHz, 300 mW, 8 kb, CMOS SRAM macro with a current sensing scheme

This paper describes the development of a 400 MHz, 8 kb, 0.4 /spl mu/m CMOS SRAM macro targeted for use in on-chip cache memories. A newly developed pipeline scheme uses a dynamic decoder and half-latches to increase speed by 10% over that of conventional synchronous pipeline SRAMs. Further, a newly developed current sensing scheme, resistant both to noise and to process deviations, contributes to a job reduction in power dissipation.<<ETX>>

Scalable bus interface for HSDPA co-processor extension

This paper presents a scalable bus developed for HSDPA co-processor extension of W-CDMA digital baseband processors. The use of two separate buses (one for control messages and one for transmission and reception data) in a multimaster bus design helps keep down bus occupancy and CPU loads. The design offers high scalability for future extension and single-chip implementation, as well as a 66% reduction in bus occupancy over that of conventional memory bus connections. Further, with the addition of a MAC accelerator, the design achieves a 45% CPU-load reduction.

Stream-access-oriented baseband signal processors for SDR

This paper presents a baseband processor developed for SDR that supports such wireless modes as WLAN, WiMAX, W-CDMA, and LTE. To achieve both the high area-efficiency of dedicated hardware and the high flexibility of DSP, we have developed a hetero-multi-processor architecture that maps each processing task either to a newly developed stream-access-oriented processor or to a parameterized hardware engine. Our design achieves 3.8 times faster baseband processing than does conventional DSP, while still maintaining high flexibility and scalability for SDR. Further, our execution controller provides faster total processing time (23% faster in an LTE design) and more flexible multi-core execution control.