Hidehiro Takata

Misleading energy and performance claims in sub/near threshold digital systems

Many of us in the field of ultra-low-Vdd processors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper investigates five major pitfalls which are often not appreciated by researchers when claiming that their circuits outperform others by working at a lower Vdd with a higher energy-efficiency. These pitfalls include: i) overlook the impacts of different technologies and different Vth definitions, ii) only emphasize energy reduction but ignore severe throughput degradation, or expect impractical pipelining depth and parallelism degree to compensate this throughput degradation, iii) unrealistically assume that memorys Vdd and energy could scale as well as standard cells, iv) use the highest temperature as the worst timing corner as in the super-threshold, but in fact negative temperature becomes much more detrimental in the sub/near threshold regime, v) pursue just-in-need Vdd to compensate effects of PVT, but without considering the high energy loss on DC-DC converters. Therefore, the actual energy benefit from using a sub/near threshold Vdd can be greatly overestimated. This work provides some design guidelines and silicon evidence to ultra-low-Vdd systems. The outlined pitfalls also shed light on future directions in this field.

Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs

Fine-grained built-in probing circuits are distributed at 120 locations on the SoC to allow continuous-time monitoring of power-supply variations. On-die high-precision sampling circuits with 800muV/100ps resolution allow probing of 26 chip-wide locations of the CPU core including SRAM modules. Analog waveforms and peak-voltage measurements show confirmation of dynamic operation-mode transitions.

Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling

Error detection FFs for dynamic voltage scaling (DVS) has been proposed. This technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. The error signal latency is shortened to 6.3%, the area and power penalties for delay buffers on short paths become 35.0% and 40.6% lower compared to the conventional DVS.

Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling

For Dynamic Voltage Scaling (DVS), we propose a novel design methodology. This methodology is composed of an error detection circuit and three technologies to reduce the area and power penalties which are the large issues for the conventional DVS with error detection. The proposed circuit, Phase-Adjustable Error Detection Flip-Flip (PEDFF), adjusts the clock phase of an additional FF for the timing error detection, based on the timing slack. 2-Stage Hold-Driven Optimization (2-SHDO) technology splits the hold-driven optimization in two stages. Slack-Based Grouping Scheme (SBGS) technology divides each timing path into appropriate groups based on the timing slack. Slack Distribution Control (SDC) technology improves the sharp distribution of the path delay at which the logic synthesis tool has relaxed the delay. We evaluate the methodology by simulating a 32-bit microprocessor in 90 nm CMOS technology. The proposed methodology reduces the energy consumption by 19.8% compared to non-DVS. The OR-trees latency is shortened to 16.3% compared to the conventional DVS. The area and power penalties for delay buffers on short paths are reduced to 35.0% and 40.6% compared to the conventional DVS, respectively. The proposed methodology with SDC reduces the energy consumption by 17.0% on another example with the sharp slack distribution by the logic synthesis compared to non-DVS.

Experimental evaluation of digital-circuit susceptibility to voltage variation in dynamic frequency scaling

Logical operations in CMOS digital integration are highly prone to fail as the amount of power-supply (PS) drop approaches to threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, in relation with instruction- level programming for logical failure analysis. Experimental measurements demonstrate that the increased susceptibility of processor operation with dynamic frequency scaling (DFS) can be mitigated through PS noise shaping.

Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature

Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25 ^°C to -40^°C, the sigma/average (σ/μ) of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that σ/μ of the gate delay is proportional to 1/<i>T</i> for the first time, where <i>T</i> is the absolute temperature.

Measurements of SRAM sensitivity against AC power noise with effects of device variation

SRAM exhibits the sensitivity of false operation against static and sinusoidal supply voltage variation. A measurement system combines direct radio frequency (RF) power injection, on-chip monitoring of voltage variation on power supply lines, and built-in self test of memory read/write operations. The bit error rate (BER) of an SRAM core exponentially increases when the lowest instantaneous voltage on the power supply line of SRAM cells during RF injection linearly decreases. Test dice on wafers at five different process corners in a 1.5 V 90 nm CMOS technology were tested. The minimum allowable voltage with BER of less than a single bit failure in average becomes smaller, thus more tolerant, when n-channel devices are at the slow corner in a conventional 6-transistor SRAM cell. The measurement technique enables to experimentally evaluate dynamic noise margin of SRAM cores in a given technology.

On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure

Switched parasitic capacitors of sleep blocks with a tri-mode power gating structure are implemented to reduce on-chip resonant supply noise in 65nm CMOS process. The proposed method achieves 46.9% and 57.9% noise reduction for wake-up noise and 130MHz periodic supply noise, respectively. The proposed method also realizes without discharging time before noise cancelling, and shows a 8.4× boost of effective capacitance value with 2.1% chip area overhead. To apply the proposed switched parasitic capacitors of sleep blocks for reducing resonant supply noise, we can save chip area for noise reduction more effectively.

Resonant supply noise canceller utilizing parasitic capacitance of sleep blocks

This paper proposes a resonant supply noise canceller utilizing parasitic capacitance of sleep blocks. It has small area penalty because we use sleep blocks for noise cancelling. Measurement results show that the test chip fabricated in a 0.18µm CMOS process achieved 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. These results make fast switching of power mode possible for dynamic voltage scaling and power gating.

A 32/spl times/24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure

We introduce the advanced rectangular styled Wallace-tree construction method. This method realizes a compact layout and high-speed operation of multiplier. A 32/spl times/24-bit multiplier-accumulator was constructed using this new method. 540 um/spl times/840 um area size and 300 MHz clock speed were achieved using 0.15 um CMOS logic process technology with flash memory.