Koji Asami

An algorithm to evaluate wide-band quadrature mixers

As wide-band wireless communications become increasingly prevalent, evaluation of balance among quadrature mixer ports, in terms of carrier phase offset, gain mismatch, and IQ skew, becomes essential. Due to the difficulty of separating skew, gain imbalance and carrier phase offset, evaluation, such as by taking measurements while calibrating, is time consuming. For this reason, test is often performed using a composite value, without separation of error factors. This paper describes an algorithm for performing accurate measurements while enabling separation among quadrature mixer gain imbalance, carrier phase offset, and skew. Thanks to the short test time of the proposed method, it can be applied during high volume production testing.

A method to improve the performance of high-speed waveform digitizing

One method for achieving high-speed waveform digitizing uses time-interleaved Analog-to-Digital Converters (ADCs). Time interleaving with two or more ADCs enables waveform digitizing at sampling rates proportionately faster than when using just one ADC. A well-known drawback of this method is that the misalignment of sampling instances degrades the achievable dynamic range. This paper proposes a solution that removes distortion caused by the alignment error with digital signal processing. Since the algorithm is realized as an extension to the ordinary FFT, the objective is achieved without significant loss of throughput.

Technique to improve the performance of time-interleaved A-D converters

Interleaving is one method of configuring a high-speed waveform digitizer. It is known that, in this method, using multiple A-D converters (ADC) enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique. This method does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead

Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity

Interleaving is one method of configuring a highspeed waveform digitizer. Degradation of the dynamic range, however, results from co-channel mismatched characteristics among the individual ADCs. Especially, mismatches of the non-linear characteristics have not been analyzed so far. This paper constructs a mathematical model, and proposes a method for correcting mismatches of both linear and non-linear characteristics using a digital signal processing technique. This method does not require any additional hardware.

Timing skew compensation technique using digital filter with novel linear phase condition

This paper describes the timing skew compensation technique using the digital filter with our novel linear phase condition. First we describe the digital filter which can set its group delay with the arbitrary fine time resolution while it maintains the linear phase characteristics; the conventional linear phase digital filter can set its group delay with the time resolution of a half of the sampling period. We will provide its structure and operation, theoretical analysis as well as simulation verification. Next we will describe the application of our proposed digital filter to compensate for timing skew in the following cases: (1) Sampling timing skew among channels in the time-interleaved ADC system. (2) I, Q-path timing skew in the single-side band (SSB) signal generator. We show its effectiveness with simulation.

An Algorithm to Improve the Performance of M-Channel Time-Interleaved A-D Converters

One method for achieving high-speed waveform digitizing uses time-interleaved A-D Converters (ADCs). It is known that, in this method, using multiple ADCs enables sampling at a rate higher than the sampling rate of the ADC being used. Degradation of the dynamic range, however, results from such factors as phase error in the sampling clock applied to the ADC, and mismatched frequency characteristics among the individual ADCs. This paper describes a method for correcting these mismatches using a digital signal processing (DSP) technique. This method can be applied to any number of interleaved ADCs, and it does not require any additional hardware; good correction and improved accuracy can be obtained simply by adding a little to the computing overhead.

WCDMA testing with a baseband/IF range AWG

WCDMA test applications using an arbitrary waveform generator (AWG) are described in this paper. A test signal generation method for the receiver section of a WCDMA handset is described with a center frequency of 161.28 MHz containing a 5 MHz spread spectrum signal. The arbitrary waveform consumes 2.6 M AWG memory locations running at 3.9 Gs/s. The 1.5 kHz primitive frequency is sufficient for generating WCDMA test chips described by the 3/sup rd/ generation partnership project (3GPP) by using modulation techniques. Other data processing for creation of the test signal include the application of a channelization code to provide orthogonal data, a scrambling code, and a root Nyquist filter for reducing the frequency content around the 161.28 MHz center. An enhancement for bit error rate tests using controllable Gaussian noise for testing receiver tolerance and acceleration of bit error rate measurements is also discussed.

Digital Compensation for Timing Mismatches in Interleaved ADCs

This paper describes a digital method of reducing timing mismatch effects in time-interleaved ADCs used in ATE systems: we use cross-correlation among channel ADC outputs to detect channel timing skew, and make successive-approximation adjustments to our proposed linear-phase-digital delay filter to compensate for the timing skew. Simulation results validate the effectiveness of the proposed method. We found that using multitone input signals with cross-correlation of outputs provided a more robust way of detecting timing skew than using a singletone input signal. Since our proposed approach is fully digital, it is reliable, and suitable for fine CMOS implementation.

Evaluation techniques of frequency-dependent I/Q imbalances in wideband quadrature mixers

As bandwidths of digital wireless communications get wider, it is essential to evaluate the I/Q imbalances among quadrature mixer ports in terms of the mismatch characteristics of the analog components in the I and Q paths and the carrier phase offset. This paper describes a technique to evaluate frequency-dependent I/Q imbalances and carrier phase offset in wideband quadrature mixers. Using an SSB stimulus, the response of a DUT with imbalances is modeled mathematically, and an identification algorithm using a unique input stimulus is constructed. The validity of this technique is confirmed using an actual WiMAX transceiver on an ATE.

Digitally-Assisted Compensation Technique for Timing Skew in ATE Systems

This paper describes timing skew adjustment techniquesin ATE systems (such as for timing skew compensation inn interleaved ADC system and an SSB signal generation system) using a digital filter with novel linear phase condition proposed in our ITC2010 paper. A conventional linear phase digital filter is an FIR filter with coefficients of odd- or even -- symmetry and whose group delay NTs/2 where N is the number of the Fir filter taps and Ts is the sampling period, its group delay time resolution is Ts/2. We have generalized the linear phase condition, and with our novel linear phase condition, the group delay time resolution can be arbitrary small, and the coefficients are not necessarily odd- or even-symmetric. In this paper we discuss several practical issues for applying our digital filter to timing skew compensation in ATE systems, such as truncation of the infinite number of taps, techniques of using window and DC gain adjustment. We also compare our digital filter with the fractional delay digital filter.