Koji Tsunoda

Reduction in the reset current in a resistive random access memory consisting of NiOx brought about by reducing a parasitic capacitance

The dependence of the relationship between the reset current Ireset and the compliance current Icomp (Ireset-Icomp characteristic) of a Pt∕NiOx∕Pt structure on the parasitic capacitance between the Pt∕NiOx∕Pt structure and a current limiter C was measured for Icomp<1mA. It was clarified that C deviated the Ireset-Icomp characteristic from the ideal linear relationship expected for C=0 and Ireset saturated at higher Icomp for larger C. This is attributed to a transient current flowing through C when the forming or set transitions occurred. The relationship of Ireset≈Icomp was maintained down to Icomp=150μA in the 1T1R cell with very small C.

Bipolar resistive switching in polycrystalline TiO2 films

Bipolar resistive switching was found in thin polycrystalline TiO2 films formed by the thermal oxidation of sputtered Ti films. With a Ag top electrode, TiO2 film, and Pt bottom electrode, bistable resistive switching with a low operating voltage and a good uniformity was observed repeatedly without an initial electrical “forming” process. This switching phenomenon might be described as the formation and rupture of a filamentary conductive path consisting of a chain of Ag atoms. The temperature dependence of the switching voltage is discussed in terms of interstitial ionic diffusion of Ag in the TiO2 matrix.

Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3 V

This paper reports on low-power and high-speed resistive switching of a Ti-doped NiO memory, which is based on the switching mechanism of the redox reactions in a filamentary conductive path. A small reset current of less than 100 muA was achieved by controlling the gate voltage of a cell transistor, which acts as an excellent current limiter in the set operation. A fast reset time of less than 5 ns was achieved by doping the Ti into the NiO film. Ti is thought to be effective to not only stabilize the reset process by forming an oxygen reservoir, but also to suppress the abnormal set phenomenon during the reset operation due to the formation of strong Ti-O bonds. Moreover, stable pulse switching with a large resistance change ratio has been successfully demonstrated using a unipolar voltage source of less than 3 V.

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Resistive random access memory consisting of NiO resistive memories and control transistors was fabricated with 0.18-mum CMOS technology. An initial forming voltage as low as 2 V was achieved with thin NiO film, and a reset current lower than 100 muA was realized by using the current limit of a selected cell transistor in the set process (1T-1R). The current level was determined by its gate voltage, resulting in the control of electrical resistance of the filamentary conductive paths in the low resistive state. Furthermore, a large voltage increase in the reset operation, which may cause an undesirable set operation, was also suppressed by a voltage-clamp transistor connected to the 1T-1R cell in series. On the basis of these proposed switching schemes, the stable pulse operation was demonstrated successfully. In addition, both nonvolatile data retention at 150degC and operation in a wide temperature range (from -40degC to 150degC) were confirmed.

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The authors report “field-programmable rectification” in crystals of rutile TiO2. A “programming” voltage is applied between two Pt electrodes on the surface of a crystal. Afterwards, current can pass in the direction of the programming voltage, but not in the reverse direction. The polarity of the rectification can be reversed by applying a programming voltage of opposite sign. The effect was observed on the (110) and (100) surfaces, but not the (001) surface. The proposed mechanism is field-induced motion of oxygen vacancies, which pile up under the negative terminal, eliminating a Schottky barrier, but leaving one at the positive terminal intact.

Reset Current of Nickel Oxide Resistive Memory Through Control of Filamentary Conductance by Current Limit of MOSFET

Spin-torque-transfer (STT) magnetoresistive random-access memory (MRAM) [1–3], a successor to field-induced magnetic switching MRAM [4,5], is an emerging non-volatile memory technology that is CMOS-compatible, scalable, and allows for high-speed access. However, two circuit-level challenges remain for STT-MRAM: potentially destructive read access due to device variation and a high-power write access. This paper presents two STT-MRAM access schemes: a negative-resistance read scheme (NRRS) that guarantees non-destructive read by design, and a negative-resistance write scheme (NRWS) that, on average, reduces the write power consumption by 10.5%. A fabricated and measured test-chip in 0.13µm CMOS confirms both properties.

Field-programmable rectification in rutile TiO2 crystals

We examined the breakdown characteristics of a 1-nm-thick MgO barrier by measuring the time dependent dielectric breakdown (TDDB) and conducting atomic force microscopy (C-AFM) observation. We found that two different local conduction modes, the percolation path and Fowler-Nordheim (F-N) tunneling, contribute to dielectric breakdown. Furthermore, the operating voltage of magnetic tunnel junctions (MTJs) for maintaining reliability over ten years against dielectric breakdown was discussed.

Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS

We engineered the interface of the MgO barrier prepared by post-oxidation of Mg metal to improve structural and electronic properties of magnetic tunnel junctions (MTJs). Drastic improvements in magnetoresistance ratio (MR) and switching voltage (Vc) with low resistance area product (RA) were achieved by inserting CoFe seed layer under the oxidized barrier. The MTJ satisfied over 1016 write cycles at 10 ns pulse under the operation voltage of 0.65 V. From these results, we have verified for the first time the hypothesis that a spin transfer torque magnetoresistance random access memory (STT-MRAM) is suitable for a non-volatile working memory.

A study of dielectric breakdown mechanism in CoFeB/MgO/CoFeB magnetic tunnel junction

We report on spin transfer torque magnetoresistance random access memory (STT-MRAM) with magnetic tunnel junctions (MTJs) that have a top-pinned stacking structure. By adopting the top-pinned structure, in which a pinned layer and an antiferromagnetic layer are deposited above the MgO tunnel barrier, we can relieve the current limitation caused by driving power asymmetry of the transistor in a 1T/1M structure without an additional current path to make a reverse connection between the transistor and the top side of the MTJs, resulting in the cell area being reduced by about half.

Demonstration of non-volatile working memory through interface engineering in STT-MRAM

In this paper, we fabricated 1T1R NiO-ReRAM test circuits based on 0.18 mum CMOS technology and observed notable suppression of I_reset by imposing current compliance I_comp using a cell transistor. Reducing the stray capacitance between Pt/NiO/Pt and the cell transistor used as a current limiter is crucial in this issue. This enabled the systematic measurement of I_comp dependence of l_reset for I_comp < 1 mA and I_reset ap I_comp was observed for 150 muA les I_comp les950 muA.