T. Sugii

Analytical models for n/sup +/-p/sup +/ double-gate SOI MOSFET's

Previously, we proposed n/sup +/-p/sup +/ double-gate SOI MOSFETs, which have n/sup +/ polysilicon for the back gate and p/sup +/ polysilicon for the front gate to enable adjustment of the threshold voltage, and demonstrated high speed operation. In this paper, we establish analytical models for this device, This transistor has two threshold voltages related to n/sup +/ and p/sup +/ polysilicon gates: V/sub th1/ and V/sub th2/, respectively. V/sub th1/ is a function of the gate oxide thickness t/sub Ox/ and SOI thickness t/sub Si/ and is about 0.25 V when t/sub Ox//t/sub Si/=5, while V/sub th2/ is insensitive to t/sub Ox/ and t/sub Si/ and is about 1 V. We also derive models for conduction charge and drain current and verified their validity by numerical analysis. Furthermore, we establish a scaling theory unique to the device, and show how to design the device parameters with decreasing gate length. We show numerically that we can design sub 0.1 /spl mu/m gate length devices with an an appropriate threshold voltage and an ideal subthreshold swing. >

beta -SiC/Si heterojunction bipolar transistors with high current gain

The combination of single-crystalline beta -SiC and Si permits the fabrication of a heterojunction bipolar transistor (HBT) in which the conventional poly-Si or single-crystalline Si emitter is replaced with a single-crystalline SiC emitter, a technique compatible with existing Si technology. A common-emitter current gain of 800 is attained with this device. The value of the ideality factor n of the base current is 1.1, which suggests that diffusion current is dominant. The large number of misfit dislocations at the SiC/Si heterojunction are ineffective as recombination centers and do not deteriorate the characteristics of the HBT.<<ETX>>

MOSFET current drive optimization using silicon nitride capping layer for 65-nm technology node

NMOSFET strain engineering using highly tensile silicon nitride capping layer was studied by way of extensive numerical simulations and device experiments. At 45nm gate length and 1V supply voltage fabricated NMOSFET delivers 1.00mA/ /spl mu/m drive current for off-state current of 40nA/ /spl mu/m and physical gate oxide thickness of 1.25nm(TEM). These data demonstrate the best up to date NMOSFET current drivability. Next, using extensive process simulations to analyze fabricated devices we developed optimization guidelines for NMOSFET strain engineering enabling us further improvement of device current drivability with reducing the gate length.

Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's

We derived a simple formula for the subthreshold swing S in double-gate (DG) SOI MOSFETs. Our formula, which depends only on a scaling device parameter, matches the device simulation results. From these results, our equations are simple and give a scaling rule for DG-SOI MOSFETs.<<ETX>>

Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages

We have investigated circuit options to surpass the 1 V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different on- and off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use-from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic. Three different pass-transistor restoration schemes were simulated with the various DTMOS techniques. Results indicate that controlling the body bias can provide a substantial speed increase and that such techniques are useful over a large range of supply voltages. Process complexity and other tradeoffs associated with DTMOS logic variations are also discussed.

Ultrafast operation of V/sub th/-adjusted p/sup +/-n/sup +/ double-gate SOI MOSFET's

To optimize the V/sub th/ of double-gate SOI MOSFETs, we fabricated devices with p/sup +/ poly-Si for the front-gate electrode and n/sup +/ poly-Si for the back-gate electrode on 40-nm-thick direct-bonded SOI wafers. We obtained an experimental V/sub th/ of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 /spl mu/m long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects.<<ETX>>

Analytical threshold voltage model for short channel double-gate SOI MOSFETs

Solving a two-dimensional (2-D) Poisson equation and assuming the minimum potential determines the threshold voltage, V/sub th/, we derived a model for V/sub th/ of short channel double-gate SOI MOSFETs, and verified its validity by comparing with numerical data. We evaluated the threshold voltage lowering, /spl Delta/V/sub th/, and subthreshold swing (S-swing) degradation with decreasing gate length L/sub G/, and showed that we can design a 0.05-/spl mu/m-L/sub G/ device with /spl Delta/V/sub th/ of less than 50 mV and an S-swing of less than 70 mV/decade if 10-nm-thick SOI is available.

Excimer laser enhanced nitridation of silicon substrates

Silicon direct nitridation has been successfully done using purified ammonia gas and an ArF excimer laser (λ=193 nm). Direct nitride films were grown at a substrate temperature of 400 °C and a laser pulse energy of 15 mJ/pulse cm2. As far as Auger signal intensities are concerned, there is little difference between the excimer laser enhanced nitrided films grown at 400 °C and thermally nitrided films grown at 1000 °C. The maximum film thickness grown is limited to 2.5 nm at 400 °C by diffusion of nitridation species across the grown film. The temperature rise on the substrate surface irradiated by the laser was calculated and found to be around 50 °C. Therefore, the thermal effect of the laser irradiation is of little significance in this experiment. The photochemically dissociated products of ammonia molecules were investigated by a quadrupole mass analyzer. The photochemically generated NH2 radicals seem to enhance the nitridation.

Technology booster using strain-enhancing laminated SiN (SELS) for 65nm node HP MPUs

Strain enhancing laminated SiN (SELS) is reported for the first time. Although the same thickness and stress SiN film is used, channel strain is enhanced by multi layer deposition. This effect was investigated by our simulations and experiments. To solve wafer bending problem, we developed a new process flow which selectively forms SELS only on the nMOS gate. A high performance 37nm gate nMOSFET and 45nm gate pMOSFET (stage IV) were demonstrated with a drive currents of 1120/spl mu/A//spl mu/m and 690/spl mu/A//spl mu/m at V/sub dd/=1V/I/sub off/=100nA//spl mu/m, respectively. This is the best drive current among the recent reports.

V/sub th/ fluctuation induced by statistical variation of pocket dopant profile

This paper studies effect of pocket (halo) profile on V/sub th/ fluctuation due to statistical dopant variation by measurement and simulation. A pocket profile significantly enhances V/sub th/ fluctuation by a factor of >15% at worst even if the implantation process variations would be negligible. This is because pocket dopants shrink the area which controls V/sub th/.