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international conference on supercomputing | 1991

Parallel computer ADENART—its architecture and application

Hiroshi Kadota; Katsuyuki Kaneko; Ichiro Okabayashi; Tadashi Okamoto; T. Mimura; Yasuhiro Nakakura; Akiyoshi Wakatani; Masaitsu Nakajima; Junji Nishikawa; Koji Zaiki; Tatsuo Nogi

A new parallel computer, ADENART (previously it was called ADENA,) for numerical applications has been developed. It is composed of 256 processing elements (:PEs) and interconnection networtcHXnet.) Each PE consists of a dedicated floating-point processor VLSI whose sustained performance is 10 MFLOPS, a communication controller VLSI and locally-distributed memories. The peak performance of the system is, therefore, 2.56GFLOPS. HXnet supports two types of efficient data-transfer modes; FAST mode and SLOW mode. Both of them are useful for various applications. The practical performance of ADENART system has been evaluated by several application programs. In partial differential equation solver, the system performance was measured as 475 MFLOPS.


Memoirs of the Faculty of Engineering, Kyoto University | 1995

Parallel Programming Language Adetran

Koji Zaiki; Akiyoshi Wakatani; Tadashi Okamoto; Katsuyuki Kaneko; Tatsuo Nogi

The concept for the ADENA (Alternating Direction Edition Nexus Array) computer was created in the late 1970s by Nogi [1, 2, 3, 4, 5]. In those days, the demands of supercomputing began to grow in science and technology, and only the vector processor was widely accepted as a supercomputer, while the ILLIAC-IV, an early parallel computer, was already destined to retire. Nogi had a perspective that the vector processor might be replaced or strengthened by parallel processing facilities in the next generation, and thought that it would be very important to get a new, more sophisticated parallel machine based upon some new ideas specifically dedicated to number-crunching scientific computation. Seeing the decline of the ILLIAC-IV, he considered that a parallel computer should not be based only upon the computational style of any explicit schemes for PDEs(Partial Differential Equations), as firstly imagined by L. F. Richardson, a famous meteorologist, and later by adherents to his idea, including the developers of the ILLIAC-IV. Nogi considered that it might be better to avoid any grid architecture of processors. We already had some excellent implicit schemes that were clearly more efficient than any explicit ones on conventional machines and were hence becoming accepted for many complex application problems, even though these implicit schemes were considered, at first glance, inefficient for parallel processing.


Archive | 1991

Processor scheduling method for iterative loops

Koji Zaiki


Archive | 1989

Dual port memory device with tag bit marking

Koji Zaiki


Archive | 1992

Apparatus for detecting possibility of parallel processing and method thereof and a program translation apparatus utilized therein

Koji Zaiki


Archive | 1995

Video-on-demand system uses adjusting positions of slots in a slot table to address additional image data distribution request from terminal devices

Tadashi Okamoto; Koji Zaiki; Shinji Sasaki; Shinji Furuya


Archive | 1994

Device and method for parallelizing compilation optimizing data transmission

Koji Zaiki


Archive | 1997

Instruction prefetching apparatus and instruction prefetching method for processing in a processor

Koji Zaiki; Tetsuya Tanaka


Archive | 1997

Instruction prefetching apparatus and instruction prefetching method

Tetsuya Tanaka; Koji Zaiki


Archive | 1989

Data buffer device using first-in first-out memory and data buffer array device

Katsuyuki Kaneko; Satoshi Gokita; Koji Zaiki

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