Konstantin Shibin

Effective Scalable IEEE 1687 Instrumentation Network for Fault Management

The infrastructure of IJTAG can be utilized during operation to detect errors and make appropriate fault handling. This article describes an architecture where error latency and automation are important requirements.

Asynchronous Fault Detection in IEEE P1687 Instrument Network

The paper describes asynchronous fault detection in silicon chips with network of embedded instruments based on IEEE P1687 IJTAG. This technique allows faster fault detection and localization by using asynchronous signal propagation from instruments to instrumentation network controller. The additional hardware is described, scenarios of operation including multiple simultaneous fault detection and localization are analysed.

On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs

Semiconductor products manufactured with latest and emerging processes are increasingly prone to wear out and aging. While the fault occurrence rate in such systems increases, the fault tolerance techniques are becoming even more expensive and one cannot rely on them alone. In addition to mitigating/correcting the faults, the system may systematically monitor, detect, localize, diagnose and classify them (manage faults). As a result of such fault management approach, the system may continue operating and degrade gracefully even in case if some of the systems resources become unusable due to intolerable faults. This works proposes a fault classification and handling methodology that fits to an event-driven on-line fault monitoring, signaling and management architecture based on IEEE1687 IJTAG and suitable for a modern complex SoC with many heterogeneous cores.

Virtual reconfigurable scan-chains on FPGAs for optimized board test

This paper presents a method for optimization of board-level scan-test with the help of reconfigurable scan-chains (RSCs) implemented in a programmable logic of FPGA. Despite that the RSC concept is a well-known solution for scan-based test time reduction, the usage of RSC may lead to un-acceptable hardware overhead. In our work, we are targeting a completely new approach of exploiting on-board FPGA resources that being unconfigured are typically available during the manufacturing test phase for carrying out tests using temporarily implemented virtual RSC structures. As the allocated FPGA logic is re-claimed for functional use after the test is finished, the presented method delivers all the advantages of RSCs at no extra HW cost. Experimental results show that the proposed virtual RSCs can fit into all available commercial FPGAs providing a significant overall test time reduction in comparison with traditional Boundary Scan approach.

Designing reliable cyber-physical systems overview associated to the special session at FDL'16

CPS, that consist of a cyber part – a computing system – and a physical part – the system in the physical environment – as well as the respective interfaces between those parts, are omnipresent in our daily lives. The application in the physical environment drives the overall requirements that must be respected when designing the computing system. Here, reliability is a core aspect where some of the most pressing design challenges are: monitoring failures throughout the computing system, determining the impact of failures on the application constraints, and ensuring correctness of the computing system with respect to application-driven requirements rooted in the physical environment. This paper provides an overview of techniques discussed in the special session to tackle these challenges throughout the stack of layers of the computing system while tightly coupling the design methodology to the physical requirements.

Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures

This paper presents a method for optimization of board-level scan test with the help of reconfigurable scan-chains (RSCs) implemented in a programmable logic of FPGA. Despite that the RSC concept is a well-known solution for scan-based test time reduction, the usage of RSC may lead to un-acceptable hardware overhead. In our work, we are targeting a completely new approach of exploiting on-board FPGA resources that being unconfigured are typically available during the manufacturing test phase for carrying out tests using temporarily implemented virtual RSC structures. As the allocated FPGA logic is re-claimed for functional use after the test is finished, the presented method delivers all the advantages of RSCs at no extra hardware cost. Experimental results show that the proposed virtual RSCs can fit into all available commercial FPGAs providing a significant test time reduction in comparison with state-of-the-art Boundary Scan test tecnique.

Designing Reliable Cyber-Physical Systems

Cyber-physical systems, that consist of a cyber part—a computing system—and a physical part—the system in the physical environment—as well as the respective interfaces between those parts, are omnipresent in our daily lives. The application in the physical environment drives the overall requirements that must be respected when designing the computing system. Here, reliability is a core aspect where some of the most pressing design challenges are: monitoring failures throughout the computing system, determining the impact of failures on the application constraints, and ensuring correctness of the computing system with respect to application-driven requirements rooted in the physical environment.

Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure

Editor’s note: Motivated by the need to tolerate faults, this paper presents a complete fault management solution that includes fault detection and categorization, maintaining a map of faults, and modified scheduling and application algorithms for using healthy resources only. As the system maintains fairly sophisticated models of itself regarding faulty and healthy resources, it constitutes a good example of specialized self-awareness. —Axel Jantsch, TU Wien