Kosei Tamiya
Olympus Corporation
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Featured researches published by Kosei Tamiya.
international solid-state circuits conference | 2013
Sunyoung Kim; Long Yan; Srinjoy Mitra; Masato Osawa; Yasunari Harada; Kosei Tamiya; C. Van Hoof; Refet Firat Yazicioglu
The accurate recognition of multiple intra-cardiac signals is becoming more and more important for Cardiac Resynchronization Therapy (CRT) and for the analysis of the intra-thoracic fluid status [1, 2]. Robust and accurate Heart-Rate (HR) monitoring at the right/left ventricles and the right atrium is essential for an implantable cardiac pacemaker system (Fig. 16.9.1), and ultra-low power consumption is needed. In addition, an accurate motion sensor and thoracic impedance measurement can acquire valuable additional information in clinical research on the intra-cardiac rhythm analysis. As shown in Fig. 16.9.2, our proposed Analog Signal Processor (ASP) IC consists of 3 power-efficient intra-cardiac signal readout channels. Each channel is equipped with a low-power QRS feature extraction unit and an ECG processor in parallel. The ASP also provides an ultra-low-power readout circuit for an external accelerometer (RA). In addition, two quadrature bio-impedance readout channels are used together with a digitized sinusoidal current generator in order to implement an accurate and wide dynamic range bio-impedance measurement. The ASP improves the state of the art by integrating a power-efficient means of QRS feature extraction for detecting Ventricular Fibrillation (VF), and a wide dynamic range bio-impedance readout.
IEEE Transactions on Biomedical Circuits and Systems | 2013
Long Yan; Julia Pettine; Srinjoy Mitra; Sunyoung Kim; Dong-Woo Jee; Hyejung Kim; Masato Osawa; Yasunari Harada; Kosei Tamiya; Chris Van Hoof; Refet Firat Yazicioglu
A low-power analog signal processing IC is presented for the low-power heart rhythm analysis. The ASIC features 3 identical, but independent intra-ECG readout channels each equipping an analog QRS feature extractor for low-power consumption and fast diagnosis of the fatal case. A 16-level digitized sine-wave synthesizer together with a synchronous readout circuit can measure bio-impedance in the range of 0.1-4.4 kΩ with 33 mΩrms resolution and higher than 97% accuracy. The proposed 25 mm2 ASIC consumes only 13 μA from 2.2 V. It is a highly integrated solution offering all the functionality of acquiring multiple high quality intra-cardiac signals, requiring only a few limited numbers of external passives.
international solid-state circuits conference | 2014
Long Yan; Pieter Harpe; Masato Osawa; Yasunari Harada; Kosei Tamiya; Chris Van Hoof; Refet Firat Yazicioglu
Ultra-low power consumption and miniature size are by far the most important design requirements for implantable pacemakers. In order to guarantee a long life span of the device, saving power in the sensing IC is a primary concern as cardiac rhythm disorders must be continuously monitored [1]. Shifting the functionality of QRS-band power parameter extraction to the analog domain can reduce system-level power consumption of heartbeat detection significantly through minimizing computational complexity of the DSP [2,3]. In addition, current biomedical ICs still require further improvement of power efficiency as their analog back ends consume significant power [2-4]. For low-power means, the presented analog signal processor (ASP) introduces a power-efficient analog feature extraction, a current-multiplexed ADC driver and a flexible ADC. This advances the state of the art by reducing the power consumption of the ASP below 1μW without compromising other specs, such as input SNR >70dB, CMRR >90dB, PSRR >80dB, and enables low-power heartbeat detection for implantable pacemakers.
IEEE Transactions on Biomedical Circuits and Systems | 2014
Long Yan; Pieter Harpe; Venkata Rajesh Pamula; Masato Osawa; Yasunari Harada; Kosei Tamiya; Chris Van Hoof; Refet Firat Yazicioglu
A sub- μW ECG acquisition IC is presented for a single-chamber leadless pacemaker applications. It integrates a low-power, wide dynamic-range ECG readout front end together with an analog QRS-complex extractor. To save ASIC power, a current-multiplexed channel buffer is introduced to drive a 7 b-to-10 b self-synchronized SAR ADC which utilizes 4 fF/unit capacitors. The ASIC consumes only 680nA and achieves CMRR >90 dB, PSRR >80 dB, an input-referred noise of 4.9 μVrms in a 130 Hz bandwidth, and has rail-to-rail DC offset rejection. Low-power heartbeat detections are evaluated with the help of the ASIC acquiring nearly 20,000 beats across 10 different records from the MIT-BIH arrhythmia database. In the presence of muscle noise, both the average Sensitivity (Se) and Positive Predictivity (PP) show more than 90% when the input SNR >6 dB.
Archive | 2008
Hideo Adachi; Katsuhiro Wakabayashi; Kosei Tamiya; Masaaki Amikura; Kazuya Matsumoto; Ryo Ohta; Mamoru Hasegawa; Hiroshi Ito
Archive | 2014
Yasuhiro Komiya; Kosei Tamiya
Archive | 2007
Hitoshi Tsuchiya; Masato Osawa; Kosei Tamiya; Tatsuya Takei; Mitsutomo Kariya; Tetsuo Kikuchi; Koichi Nakata
Archive | 2013
Yasuhiro Komiya; 小宮 康宏; Kosei Tamiya; 公成 田宮
Archive | 2006
Hideo Adachi; Katsuhiro Wakabayashi; Kosei Tamiya; Masaaki Amikura; Kazuya Matsumoto; Ryo Ohta; Mamoru Hasegawa; Hiroshi Ito
Archive | 2016
Masao Sambongi; Kosei Tamiya