Spyros Blionas

Instruction level energy modeling for pipelined processors

A new method for creating instruction level energy models for pipelined processors is introduced. This method is based on measuring the instantaneous current drawn by the processor during the execution of the instructions. An appropriate instrumentation set up was established for this purpose. According to the proposed method the energy costs (base and inter-instruction costs) are modeled in relation to a reference instruction (e.g. NOP). These costs incorporate inter-cycle energy components, which cancel each other when they are summed to produce the energy consumption of a program resulting in estimates with high accuracy. This is confirmed by the results. Also the dependencies of the energy consumption on the instruction parameters (e.g. operands, addresses) are studied and modeled in an efficient way.

Realization of wireless multimedia communication systems on reconfigurable platforms

Wireless multimedia communication systems become increasingly more computational intensive and demand for higher flexibility. The realization of these systems on reconfigurable hardware offers a good balance for these requirements. In this paper the suitability of commercially available reconfigurable hardware platforms for the target application domain is evaluated. Based on this evaluation a heterogeneous partly reconfigurable system-on-chip platform is identified as ideal implementation platform for the targeted systems. Systems from different target domains are analysed and different cases where the inclusion of reconfigurable hardware in their realizations would lead to improved quality in terms of implementation efficiency and flexibility are identified, Design methodology requirements for the realization of systems from the target application domain on the targeted platform are analysed and issues not covered by existing methodologies are identified. The principles of a methodology handling these open issues are described. Results from the prototyping of different systems are also presented and show the potentials of a reconfigurable hardware platform, which in the future will lead to reduced costs and increased flexibility of the wireless multimedia communication systems.

Power Optimization Methodology for Multimedia Applications Implementation on Reconfigurable Platforms

A methodology for the power-efficient implementation of multimedia kernels based on reconfigurable hardware (FPGA) is introduced. The methodology combines various types of algorithmic transformations and high-level memory hierarchy exploration with register-transfer level design and implementation. An FPGA with an external memory was used for obtaining experimental results which prove the viability of the methodology. Comparisons among implementations with and without this optimization, prove that great power efficiency is achieved.

Architecture of a Consumer Lab-on-Chip for Pharmacogenomics

This paper presents the architecture of the electronic detection and data processing (analysis) part, of a lab-on-chip (LoC) device. The LoC consists of a microfluidics part for the sample preparation and hybridization, a micro-system part including the sensors for the hybridization electronic detection and finally a processing part for the data analysis and the consumer interface for results presentation. Consumers will use such LoCs for identifying the appropriate cluster of a pharmacogenomic medicine based on the gene analysis results and optimize the effectiveness of the drug or determine whether they belong to a group of patients who would suffer severe side effects.

Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size

The overall operation of a Direct Digital Frequency Synthesizer (DDFS) is based on a look up table method, which performs functional mapping from phase to sine amplitude. The spectral purity of the conventional DDFS is determined by the resolution of the values stored in the sine table ROM. However, large ROM storage means higher power consumption, lower reliability, lower speed and increased costs. The novel design and implementation of a DDFS, with reduced memory size, is introduced. Using new technique, the resulting architecture can be realized by smaller number of gates (i.e. less hardware complexity) than existing ones. Describing the proposed architecture, with the hardware description language VHDL, we can generate plethora of alternative realizations in terms of the number of inputs and output bits, the memory size, the number of gates, the memory segmentation parameters, and the spectral purity. In other words, the designer can perform extensive architecture exploration to reach his/her optimal solution.

FPGA implementation of an MLSE equalizer in 10Gb/s optical links

In this paper, an FPGA implementation of a Maximum Likelihood Sequence Estimator (MLSE) is proposed, in the context of Intensity Modulated Direct Detection optical communications links operating at 10Gb/s, when non-return to zero on-off keyed transmission is employed. A forward processing, sliding window systolic architecture is adopted for the implementation of the Viterbi algorithm (VA), used for the efficient computation of the sequence detection in the MLSE approach. The proposed VA architecture is implemented using synthesisable VHDL code. VA decoders of up to 32 states operating at the rate of 10Gb/s can be accommodated, when the targeted hardware is the Xilinx Virtex 7 XC7VX690T-2 FPGA chip. A peak processing rate of 56Gb/s is achieved for a 4 states VA decoder.

A Multi-level Validation Methodology for Wireless Network Applications *

This paper presents the validation methodology established and ap-plied during the development of a wireless LAN application. The target of the development is the implementation of the hardware physical layer of the HIPERLAN/2 wireless LAN protocol and its interface with the upper layers. The implementation of the physical layer (modem) has been validated in two different levels. First, at the functional level, the modem was validated by a high-level UML model. Then, at the implementation level, a new validation framework drives the validation procedure at three different sub-levels of de-sign abstraction (numerical representation, VHDL coding, FPGA-based proto-typing). Using this validation methodology, the prototype of the HIPERLAN/2 modem has been designed and validated successfully.

A reusable IP FFT core for DSP applications

In this paper, reusable intellectual property cores for the efficient implementation of digital signal processing (DSP) applications such as wireless LAN are presented. More specifically, a split-radix FFT algorithm implementation architecture, whose applicability for these communication systems has been proven, was designed using reusable VHDL. Four different implementations of the split-radix butterfly element are presented. These different butterfly elements allow tradeoffs between performance, power consumption and hardware complexity. Finally, for demonstration purpose, comparison results of split-radix and radix-4 implementations on Virtex and Virtex-II devices are also presented.

Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations

A run-time reconfiguable array of multipliers architecture is introduced. The novel multiplier can be easily reconfigured to trade bitwidth for array size, thus maximizing the utilization of available hardware, multiply signed or unsigned data, and uses part of its structure when needed. The proposed reconfigurable circuit consists of an array of m×m multipliers, a few arrays of adders each adding three numbers, and switches. Also small blocks for the implementation of the reconfiguration capabilities, mentioned above, consist of adders, multiplexers, inverters, coders and registers. The circuit reconfiguration can be done dynamically through using only a few control bits. The architecture design of the reconfigurable multiplier, with hardware equivalent to one 64×64 bit high precision multiplier, which can be dynamically reconfigured to produce an array of the products in different forms is described in detailed manner.

Evaluation of silicon and polymer substrates for fabrication of integrated microfluidic microsystems for DNA extraction and amplification.

This paper is presenting two different alternatives for the DNA extraction and amplification that will be carried out by two competitive research projects developing bioanalytical microsystems with microfluidics. The first project will develop the microfluidics part on polymer material and the other one on silicon. The polymer approach is currently under development based on a modular microfluidic architecture aimed to simplify the process of designing and building such a microsystem device. A silicon alternative is about to start and is expected to decrease packaging costs of the microsystem allowing future manufacturability of the device