Panagiotis Merakos

Low power synthesis of sum-of-products computation

Novel techniques for the power efficient synthesis of sum-of-product computations are presented. Simple and efficient heuristics for scheduling and assignment are described. Different partly static cost functions are proposed to drive the synthesis tasks. The proposed cost functions target the power consumption either in the buses connecting the functional units with the storage elements or inside the functional units. The partly static nature of the proposed cost functions reduces the time of the synthesis procedure. Experimental results from different relevant digital signal processing algorithmic kernels prove that the proposed synthesis techniques lead to significant power savings.

Novel techniques for bus power consumption reduction in realizations of sum-of-product computation

Novel techniques for power-efficient implementation of sum of product computation are presented. The proposed techniques aim at reducing the switching activity required for the successive evaluation of the partial products, in the busses connecting the storage elements where data and coefficients are stored to the functional units. This is achieved through reordering the sequence of evaluation of the partial products. Heuristics based on the traveling salesman problem are proposed to perform the reordering for different categories of algorithms. Information related to both data (dynamic) and coefficients (static) is used to drive the reordering. Experimental results from the application of the proposed techniques on several signal-processing algorithms have proven that significant switching activity savings can be achieved.

A novel methodology for power consumption reduction in a class of DSP algorithms

In this paper a novel approach for low power realization of DSP algorithms that are based on inner product computation is proposed. Inner product computation between data and coefficients is a very common computational structure in DSP algorithms. The proposed methodology is based on an architectural transformation that reorders the sequence of evaluation of the partial products forming the inner products. The total Hamming distance of the sequence of coefficients, which are known before realization, is used as the cost function driving the reordering. The reordering of computation reduces the switching activity at the inputs of the computational units. Experimental results show that the proposed methodology leads to significant savings in switching activity and thus in power consumption.

Novel vector quantization based algorithms for low-power image coding and decoding

In this paper, a novel scheme for low-power image coding and decoding based on vector quantization is presented. The proposed scheme uses small codebooks, and block transformations are applied to the codewords during coding. Using small codebooks, the proposed scheme has reduced memory requirements in comparison to classical vector quantization. The transformations applied to the codewords extend computationally the small codebooks compensating for the quality degradation introduced by the small codebook size. Thus the coding task becomes computation-based rather than memory-based, leading to significant power savings since memory-related power consumption forms the major part of the total power consumption of a system. Since the parameters of the transformations depend on the image block under coding, the small codebooks are dynamically adapted to the specific block under coding leading to acceptable image qualities. The proposed scheme leads to power savings of a factor of 10 in coding and of a factor of 3 in decoding, at least in comparison to classical full-search vector quantization. The main factor affecting both image quality and power consumption is the size of the codebook that is used.

Power efficient data path synthesis of sum-of-products computations

Techniques for the power efficient data path synthesis of sum-of-products computations between data and coefficients are presented. The proposed techniques exploit specific features of this type of computations. Efficient heuristics for the scheduling and assignment tasks, based on the concept of the Traveling Salesmans Problem, are described. Different cost functions are proposed to drive the synthesis tasks. The proposed cost functions target the power consumption either in the interconnect buses or in the functional units. Experimental results from different relevant digital signal processing algorithmic kernels prove that the proposed synthesis techniques lead to significant power savings.

A novel transformation for reduction of switching activity in FIR filters implementation

A novel high level transformation for low power implementation of FIR filters is presented. The new idea is the reordering of the filter coefficients aiming at the minimisation of the switching activity. As a measure of the switching activity the Hamming distance (HD) between successive coefficients, stored in a memory, is used. The transformation can be incorporated both in application specific architectures and in general purpose programmable architectures. The reordering of the N coefficients, for the HD optimisation of their sequence, can be modelled by a travelling salesman problem (TSP), which is a well known NP-complete problem. A novel heuristic algorithm for a fast and accurate solution to this problem is proposed. Experimental results show that the proposed technique leads to significant power savings in terms of switching activity reduction.

A novel algorithm for low-power image and video coding

A novel scheme for low-power image and video coding and decoding is presented. It is based on vector quantization, and reduces its memory requirements, which form a major disadvantage in terms of power consumption. The main innovation is the use of small codebooks, and the application of simple but efficient transformations to the codewords during coding to compensate for the quality degradation introduced by the small codebook size. In this way, the small codebooks are computationally extended, and the coding task becomes computation based rather than memory based, leading to significant power consumption reduction. The parameters of the transformations depend on the image block under coding, and thus the small codebooks are dynamically adapted each time to this specific image block, leading to image qualities comparable to or better than those corresponding to classical vector quantization. The algorithm leads to power savings of a factor of 10 in coding and of a factor of 3 in decoding at least, in comparison to classical full-search vector quantization. Both image quality and power consumption highly depend on the size of the codebook that is used.

Low power synthesis of sum-of-products computation (poster session)

Novel techniques for the power efficient synthesis of sum-of-product computations are presented. Simple and efficient heuristics for scheduling and assignment are described. Different partly static cost functions are proposed to drive the synthesis tasks. The proposed cost functions target the power consumption either in the buses connecting the functional units with the storage elements or inside the functional units. The partly static nature of the proposed cost functions reduces the time of the synthesis procedure. Experimental results from different relevant digital signal processing algorithmic kernels prove that the proposed synthesis techniques lead to significant power savings.

Power Efficient Vector Quantization Design Using Pixel Truncation

Vector quantization image encoding requires a huge amount of computation and thus of power consumption. In this paper a novel method is proposed for the reduction of the power consumption of vector quantization image processing by truncating the least significant bits of the image pixels and the codewords elements during the nearest neighbor computation. Experimental results prove that at least 3 pixels/elements bits can be truncated without affecting the picture quality. This results in an average 65% reduction of bus power consumption and in an average 62% reduction of the power consumed in major data path blocks.

Trade-Off Analysis of a Low-Power Image Coding Algorithm

In this paper, a novel algorithm for low-power image coding and decoding is presented and the various inherent trade-offs are described and investigated in detail. The algorithm reduces the memory requirements of vector quantization, i.e., the size of memory required for the codebook and the number of memory accesses by using small codebooks. This significantly reduces the memory-related power consumption, which is an important part of the total power budget. To compensate for the loss of quality introduced by the small codebook size, simple transformations are applied on the codewords during coding. Thus, small codebooks are extended through computations and the main coding task becomes computation-based rather than memory-based. Each image block is encoded by a codeword index and a set of transformation parameters. The algorithm leads to power savings of a factor of 10 in coding and of a factor of 3 in decoding, at least in comparison to classical full-search vector quantization. In terms of SNR, the image quality is better than or comparable to that corresponding to full-search vector quantization, depending on the size of the codebook that is used. The main disadvantage of the proposed algorithm is the decrease of the compression ratio in comparison to vector quantization. The trade-off between image quality and power consumption is dominant in this algorithm and is mainly determined by the size of the codebook.