Kou Chen Liu

A deep submicron Si/sub 1-x/Ge/sub x//Si vertical PMOSFET fabricated by Ge ion implantation

We report a deep submicron vertical PMOS transistor using strained Si/sub 1-x/Ge/sub x/ channel formed by Ge ion implantation and solid phase epitaxy. These vertical structure Si/sub 1-x/Ge/sub x//Si transistors can be fabricated with channel lengths below 0.2 /spl mu/m without using any sophisticated lithographic techniques and with a regular MOS process. The enhancement of hole mobility in a direction normal to the growth plane of strained Si/sub 1-x/Ge/sub x/ over that of bulk Si has been experimentally demonstrated for the first time using this vertical MOSFET. The drain current of these vertical MOS devices has been found to be enhanced by as much as 100% over control Si devices. The presence of the built-in electric field due to a graded SiGe channel has also been found to be effective in further enhancement of the drive current in implanted-channel MOSFETs.

Vertical P-MOSFETs with heterojunction between source/drain and channel

The growth of high quality strained SiGe-Si and SiGeC-Si heterostructures allows incorporation of band gap engineering into Si technology, which can be used to improve device characteristics. A heterojunction MOSFET (HJMOSFET) structure has been proposed in which the large valence band offset at SiGe-Si heterojunctions reduces the punchthrough and DIBL for P-MOSFETs (Hareland et al, 1993). Vertical MOSFETs allow more freedom in terms of band gap engineering, and the channel length is not limited by the lithography (Liu et al, 1998). In this paper, we show experimentally that the heterojunction at the source can be used to suppress the floating body effect and short channel effect. Vertical P-MOSFETs with strained SiGe and SiGeC sources have been fabricated with 60-75 nm effective channel lengths. The electrical characteristics of the devices are compared with those of control Si devices and with simulation results.

Hole and electron mobility enhancement in strained SiGe vertical MOSFETs

We have fabricated strained SiGe vertical P-channel and N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) by Ge ion implantation and solid phase epitaxy. No Si cap is needed in this process because Ge is implanted after gate oxide growth. The vertical MOSFETs are fabricated with a channel length below 0.2 /spl mu/m without sophisticated lithography and the whole process is compatible with a regular CMOS process. The enhancement for the hole and electron mobilities in the direction normal to the growth plane of strained SiGe over that of bulk Si has been demonstrated in this vertical MOSFET device structure for the first time. The drain current for the vertical SiGe MOSFETs has been found to be enhanced by as much as 100% over the Si control devices and the drain current for the vertical SiGe NMOSFETs has been enhanced by 50% compared with the Si control de, ices on the same wafer. The electron mobility enhancement in the normal direction is not as significant as that for holes, which is in agreement with theoretical predictions.

Enhanced mobility PMOSFETs using tensile-strained Si/sub 1-y/C y layers

We demonstrate for the first time that carbon incorporation in Si epitaxial layers may be an alternative method to deposit enhanced mobility tensile-strained Si MOSFET channel layers directly on a silicon substrate, thereby eliminating the need to deposit a thick relaxed SiGe buffer layer, from which dislocations and other defects can propagate to the channel region. The fabrication and electrical properties of PMOSFETs with Si/sub 1-y/C/sub y/ alloy channel layers are reported in this paper for the first time. It is found that small amounts of C in Si films can produce high quality epitaxial material. PMOSFETs fabricated on these layers demonstrate enhanced hole mobility over that of control Si.

Band alignments in sidewall strained Si/strained SiGe heterostructures

Abstract The band edge shift and splitting in an orthorhombically strained Si (OS-Si) layer grown on the sidewall of a compressively strained SiGe (CS-SiGe) alloy is calculated in terms of model-solid theory. Both the valence and conduction band edges of the OS-Si are predicted to be lower than those of CS-SiGe. Compared with tensily strained Si grown on a relaxed SiGe alloy, the conduction band offset between OS-Si and CS-SiGe is smaller, while the valence band offset is larger.

A novel sidewall strained-Si channel nMOSFET

We fabricated a novel vertical sidewall strained-Si device without relaxed SiGe buffer layers in this work. The electrical performance has been characterized using C-V and I-V measurement. TEM pictures show a high quality crystalline tensile-strained-Si layer grown on the sidewall of a compressively-strained SiGe layer. The transconductance measurements of sidewall-tensile-strained Si n-MOSFETs exhibit the role of enhanced electron mobility as tensile strain increases. In addition to device results, theoretical sidewall conduction and valence band offset calculations, relative to the strained SiGe layer, are also presented.

Electron mobility enhancement in strained SiGe vertical n-type metal–oxide–semiconductor field-effect transistors

We have fabricated strained SiGe vertical n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) by Ge ion implantation and solid phase epitaxy. No Si cap is needed in this process because Ge is implanted after gate oxide growth. The vertical MOSFETs are fabricated with a channel length below 0.2 μm without sophisticated lithography and the whole process is compatible with a regular complementary metal–oxide–semiconductor process. The drive current for these devices has been observed to be enhanced by 50% compared with Si control devices on the same wafer. Electron mobility enhancement in the out-of-plane direction for the strained SiGe layer was demonstrated in this study.

Bandgap engineering in vertical P-MOSFETs

Abstract Bandgap engineering in vertical P-MOSFETs has been investigated in view of suppressing the short channel effects, floating body effect, and improving the drive current. SiGe source heterojunction P-MOSFETs have been used to suppress the short channel effects for sub-100 nm devices. While the leakage is reduced, the drive current is also reduced due to the use of a heterojunction. In this paper, we discuss a SiGe source heterojunction vertical P-MOSFET with a few nanometers thick Si cap. With this device structure, the absence of the heterojunction-induced potential barrier right below the oxide interface improves the drive current substantially while the drain induced barrier lowering effect and floating body effect are still suppressed. To further improve the drive current of the device, a SiGe/Si cap was added to the SiGe heterojunction P-MOSFET. We call this device a high mobility heterojunction MOSFET (HMHJT). Compared with the Si control device, the HMHJT has higher drive current and less off-state current at the same time.

Enhancement of drain current in vertical SiGe/Si PMOS transistors using novel CMOS technology

CMOS devices are being scaled for density and speed. However, scaling gate length is impeded by lithographic technology and scaling device width is limited by low hole mobility in PMOS transistors. In vertical MOS transistors, however, lithography does not limit the channel length. Current drive in PMOS devices may also be increased by use of a SiGe channel. In fact, the hole mobility in strained SiGe normal to the growth plane is predicted to be significantly larger than in its unstrained counterpart. Therefore, we propose vertical Si/sub 1-x/Ge/sub x//Si PMOS and Si NMOS transistors and demonstrate (1) 100% increase of drive current in a vertical SiGe PMOS device, (2) the first experimental evidence of the enhancement of out-of-plane hole mobility in a vertical PMOSFET, and (3) experimental results for vertical NMOS devices, thus exhibiting the promise of vertical SiGe/Si CMOS.

Enhanced hole mobilities in tensile-strained Si/sub 1-y/C/sub y/ alloy PMOSFETs

The incorporation of C in Si epitaxial layers can used as an alternative method to deposit tensile-strained Si layers directly on a silicon substrate, for obtaining improved hole transport behavior in the valence band. The proposed method to produce tensile-strained layers is attractive because it eliminates the need to deposit a thick relaxed SiGe buffer layer. Additionally, the elimination of this relaxed buffer layer alloys the concern over dislocations and other defects propagating to the channel region. The fabrication and transport properties of PMOSFETs utilizing a strained-engineered Si/sub 1-y/C/sub y/ channel are reported for the first time in this paper.