Sandeep K. Oswal

A deep submicron Si/sub 1-x/Ge/sub x//Si vertical PMOSFET fabricated by Ge ion implantation

We report a deep submicron vertical PMOS transistor using strained Si/sub 1-x/Ge/sub x/ channel formed by Ge ion implantation and solid phase epitaxy. These vertical structure Si/sub 1-x/Ge/sub x//Si transistors can be fabricated with channel lengths below 0.2 /spl mu/m without using any sophisticated lithographic techniques and with a regular MOS process. The enhancement of hole mobility in a direction normal to the growth plane of strained Si/sub 1-x/Ge/sub x/ over that of bulk Si has been experimentally demonstrated for the first time using this vertical MOSFET. The drain current of these vertical MOS devices has been found to be enhanced by as much as 100% over control Si devices. The presence of the built-in electric field due to a graded SiGe channel has also been found to be effective in further enhancement of the drive current in implanted-channel MOSFETs.

Novel SiGeC channel heterojunction PMOSFET

The fabrication and characterization of heterojunction PMOSFETs with strain-engineered Si/sub 1-x-y/Ge/sub x/C/sub y/ channel is reported for the first time. The study has demonstrated the performance enhancement of partially strain compensated Si/sub 0.793/Ge/sub 0.2/C/sub 0.007/ MOSFET over fully-strained metastable Si/sub 0.8/Ge/sub 0.2/ channel. Complete strain compensation by incorporating higher amounts of C (Ge-to-C ratio=10:1), however, results in the degradation of device characteristics as compared to the Si/sub 1-x/Ge/sub x/ sample.

Heterostructure P-channel metal–oxide–semiconductor transistor utilizing a Si1−x−yGexCy channel

The dc characteristics of Si1−x−yGexCy P-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) were evaluated between room temperature and 77 K and were compared to those of Si and Si1−xGex PMOSFETs. The low-field effective mobility in Si1−x−yGexCy devices is found to be higher than that of Si1−xGex (grown in the metastable regime) and Si devices at low gate bias and room temperature. However, with increasing transverse fields and with decreasing temperatures, Si1−x−yGexCy devices show degraded performance. The enhancement at low gate bias is attributed to the strain stabilization effect of C. This application of Si1−x−yGexCy in PMOSFETs demonstrates potential benefits in the use of C for strain stabilization of the binary alloy.

A novel sidewall strained-Si channel nMOSFET

We fabricated a novel vertical sidewall strained-Si device without relaxed SiGe buffer layers in this work. The electrical performance has been characterized using C-V and I-V measurement. TEM pictures show a high quality crystalline tensile-strained-Si layer grown on the sidewall of a compressively-strained SiGe layer. The transconductance measurements of sidewall-tensile-strained Si n-MOSFETs exhibit the role of enhanced electron mobility as tensile strain increases. In addition to device results, theoretical sidewall conduction and valence band offset calculations, relative to the strained SiGe layer, are also presented.

Enhancement of drain current in vertical SiGe/Si PMOS transistors using novel CMOS technology

CMOS devices are being scaled for density and speed. However, scaling gate length is impeded by lithographic technology and scaling device width is limited by low hole mobility in PMOS transistors. In vertical MOS transistors, however, lithography does not limit the channel length. Current drive in PMOS devices may also be increased by use of a SiGe channel. In fact, the hole mobility in strained SiGe normal to the growth plane is predicted to be significantly larger than in its unstrained counterpart. Therefore, we propose vertical Si/sub 1-x/Ge/sub x//Si PMOS and Si NMOS transistors and demonstrate (1) 100% increase of drive current in a vertical SiGe PMOS device, (2) the first experimental evidence of the enhancement of out-of-plane hole mobility in a vertical PMOSFET, and (3) experimental results for vertical NMOS devices, thus exhibiting the promise of vertical SiGe/Si CMOS.

Sil-x-yGexCy channel heterojunction PMOSFETs

Strain-compensated Si1-x-yGexCy alloy appears attractive because it may eliminate the constraints in Si1- xGex device design involving high Ge concentrations, thicker active layers, and may allow relatively higher process temperature windows. PMOSFET devices were fabricated with partially strained Si1-x-yGexCy films with Ge-to-C ratio of 30:1 in order to preserve the valence band offset to confine holes. Bulk and epitaxial Si, Si1-xGex and completley strain-compensated Si1-x-yGexCy were also processed for comparison. An n+-poly gate PMOS process was used. The dc characteristics of the Si1-x- yGexCy PMOSFETs with channel lengths varying from 0.8 to 10 micrometer were evaluated between room temperature and 77 degrees Kelvin and were compared to those of Si and Si1-xGex PMOSFETs. The low field effective mobility in Si1-x-yGexCy devices were found to be higher than that of Si1-xGex and Si devices at low gate bias and room temperature as a result of partial strain compensation. However, with increasing transverse fields and with decreasing temperatures, Si1-x-yGexCy, we observed degradation in device performance. This enhancement at low gate bias was attributed to the strain stabilization effect of C. At higher C concentrations, degraded performance was observed. This first application of Si1-x-yGexCy in PMOSFETs demonstrates potential benefits in the use of C with the column IV heterostructure system.

SiGe/Si vertical PMOSFET device design and fabrication

As channel lengths shrink continuously to smaller dimensions in order to improve performance and packing density, lithography, isolation, power supply and short channel effects have proved to be major limitations. Recently vertical MOSFETs (VMOS), also known as surround gate transistors, or 3-D side- wall transistors have been shown to overcome these process limitations. In this paper, we review the various VMOS technologies and applications and compare the performance of these devices to planar devices. We also present a novel deep submicron vertical SiGe/Si PMOSFET fabricated by Ge implantation. The Ge was implanted in the Si vertical channel to form a strained SiGe layer to increase drive current in P channel devices. PMOS drive current can be increased by about 100% compared to Si control devices. Thus, this technology offers CMOS circuit designers the flexibility to match PMOS and NMOS current drive capabilities, which was previously limited by the difference in electron and hole mobilities in Si.

Si1-x-yGexCy channel heterojunction PMOSFETs

Strain-compensated Si1-x-yGexCy alloy appears attractive because it may eliminate the constraints in Si1- xGex device design involving high Ge concentrations, thicker active layers, and may allow relatively higher process temperature windows. PMOSFET devices were fabricated with partially strained Si1-x-yGexCy films with Ge-to-C ratio of 30:1 in order to preserve the valence band offset to confine holes. Bulk and epitaxial Si, Si1-xGex and completley strain-compensated Si1-x-yGexCy were also processed for comparison. An n+-poly gate PMOS process was used. The dc characteristics of the Si1-x- yGexCy PMOSFETs with channel lengths varying from 0.8 to 10 micrometer were evaluated between room temperature and 77 degrees Kelvin and were compared to those of Si and Si1-xGex PMOSFETs. The low field effective mobility in Si1-x-yGexCy devices were found to be higher than that of Si1-xGex and Si devices at low gate bias and room temperature as a result of partial strain compensation. However, with increasing transverse fields and with decreasing temperatures, Si1-x-yGexCy, we observed degradation in device performance. This enhancement at low gate bias was attributed to the strain stabilization effect of C. At higher C concentrations, degraded performance was observed. This first application of Si1-x-yGexCy in PMOSFETs demonstrates potential benefits in the use of C with the column IV heterostructure system.

Si 1-x-y Ge x C y channel heterojunction PMOSFETs

Strain-compensated Si1-x-yGexCy alloy appears attractive because it may eliminate the constraints in Si1- xGex device design involving high Ge concentrations, thicker active layers, and may allow relatively higher process temperature windows. PMOSFET devices were fabricated with partially strained Si1-x-yGexCy films with Ge-to-C ratio of 30:1 in order to preserve the valence band offset to confine holes. Bulk and epitaxial Si, Si1-xGex and completley strain-compensated Si1-x-yGexCy were also processed for comparison. An n+-poly gate PMOS process was used. The dc characteristics of the Si1-x- yGexCy PMOSFETs with channel lengths varying from 0.8 to 10 micrometer were evaluated between room temperature and 77 degrees Kelvin and were compared to those of Si and Si1-xGex PMOSFETs. The low field effective mobility in Si1-x-yGexCy devices were found to be higher than that of Si1-xGex and Si devices at low gate bias and room temperature as a result of partial strain compensation. However, with increasing transverse fields and with decreasing temperatures, Si1-x-yGexCy, we observed degradation in device performance. This enhancement at low gate bias was attributed to the strain stabilization effect of C. At higher C concentrations, degraded performance was observed. This first application of Si1-x-yGexCy in PMOSFETs demonstrates potential benefits in the use of C with the column IV heterostructure system.