Kouichi Muraoka

Reaction steps of silicidation in ZrO2/SiO2/Si layered structure

Reaction steps of silicidation in ZrO2/SiO2/Si layered structure have been investigated in terms of ultrahigh vacuum annealing. Comparison of 2- and 20-nm ZrO2 films at 920 °C revealed that the trigger of silicidation is the contact of ZrO2, SiO, and Si accompanying disappearance of interfacial SiO2 layer due to SiO desorption. In the contact position, a small amount of SiO gas can easily change ZrO2 to ZrSi2. Moreover, this reaction model is also applicable to the silicidation of gate polycrystalline-Si (poly-Si)/ZrO2 interface.

Investigation of Nitrogen-Originated NBTI Mechanism in SiON with High-Nitrogen Concentration

We have investigated the nitrogen-originated NBT degradation mechanism of SiON films by using SiON with high nitrogen concentration. It was found that, threshold voltage shift (DeltaVth) under NBT stress is degraded with increasing nitrogen concentration in bulk rather than that at interface. Furthermore, NBTI exponents strongly correlate with the nitrogen concentration in bulk and pre-stressed flat-band voltage shift (AVfb ini). From these experimental results, we interpret that there is an additional NBT degradation mechanism with small NBTI exponents (beta > 0.25) and this is originated by pre-existing defects due to nitrogen incorporation. Finally, from the reliability viewpoint, we propose that decreasing the defect in bulk introduced during nitridation is indispensable for the fabrication process of high nitrogen concentration SiON maintaining high reliability

Optimum structure of deposited ultrathin silicon oxynitride film to minimize leakage current

The role of oxygen inside silicon oxynitride (SiON) films respecting leakage current was investigated. We successfully controlled composition of bulk SiON film in accordance with the alloy model: (Si 3 N 4 ) x (SiO 2 ) 1-x regarding ultra thin composite SiON structure and stacked SiON/ SiO 2 structure and measured electrical properties of these SiON films. We, furthermore, studied the conduction mechanisms of the leakage current for these films by using a direct tunneling (DT) current simulation with Wentzel-Kramers-Brillouin (WKB) approximation, taking dielectric constant, band profile and effective mass into consideration. From these experiments and simulations, it was found that the leakage current of composite structure is lower than that of stacked structure, even if those structure have the same alloy ratio x. Furthermore, we found the optimum film composition to minimize DT current. The optimum structure was determined by the balance between the decrease in electron DT current and the increase in hole current due to the physical thickness and the valence band barrier height.

Determination of tunnel mass and physical thickness of gate oxide including poly-Si/SiO/sub 2/ and Si/SiO/sub 2/ interfacial transition Layers

By including poly-Si/SiO/sub 2/ and Si/SiO/sub 2/ interfacial transition (IFT) layers, an excellent agreement in terms of both C-V and J-V characteristics is obtained between the experiment and theory for both polarities of gate voltage (V/sub G/) for the first time. The highly precise physical models for gate depletion and gate accumulation bring an oxide thickness extracted from the C-V fitting in a negative V/sub G/ close to that extracted in a positive V/sub G/. It is shown that the physical oxide thickness should be regarded as a distance between the middle points inside the IFT layers in both sides of the gate oxide. In addition, it is found that the tunnel mass is independent of the gate-oxide thickness from 14 to 28 /spl Aring/. It is also shown that the oxide-thickness dependence of the tunnel mass , is ascribable to the C-V-J-V fitting only in the case of a negative polarity of V/sub G/ while neglecting the poly-Si/SiO/sub 2/ IFT layer.

Novel fabrication process to realize ultra-thin (EOT = 0.7nm) and ultra-low leakage SiON gate dielectrics

We achieved 0.73 nm EOT, 88 A/cm/sup 2/ J/sub g/, and 92% G/sub m/ of that for SiO/sub 2/ by just oxidation of SiN films. In addition, we achieved further improvement of EOT-J/sub g/ characteristics by re-nitridation process with minimum degradation of G/sub m/. EOT of 0.70 nm and J/sub g/ as 95 A/cm/sup 2/ is realized with superior suppression of boron penetration (/spl Delta/V/sub th/=0.04 V).

Numerical approach for retention characteristics of double floating-gate memories

We report on a numerical investigation in which memory characteristics of double floating-gate (DFG) structure were compared to those of the conventional single floating-gate structure, including an interference effect between two cells. We found that the advantage of the DFG structure is its longer retention time and the disadvantage is its smaller threshold voltage shift. We also provide an analytical form of charging energy including the interference effect.

Suppression of silicidation in polycrystalline-Si/ high-κ insulator/SiO2∕Si structure by helium through process

Suppression of silicidation in polycrystalline-Si (poly-Si)/ high-κ insulators (ZrO2,HfO2)∕SiO2∕Si structure by helium (He) through process which adds He gas during a poly-Si gate process was demonstrated. In Si deposition on ZrO2 and HfO2 by SiH4 flow diluted by N2 or He, surface silicidation can be suppressed by lowering of initial deposition temperature below 600 and 650°C, respectively, but thin SiO2 films are formed between Si films and these high-κ insulator surfaces without being dependent on the dilution gases. Moreover, it is found that He through process of low-temperature SiH4 flow diluted by He and high-pressure He postannealing is the most effective means of suppressing not only the thermal degradation of high-κ insulator/SiO2∕Si interface but also the silicidation of poly-Si∕SiO2/ high-κ insulator interface, whereas conventional N2 through process cannot suppress both. These results mean that high-concentration He atoms are indispensable for upper and lower SiO2∕Si interfaces. It is supposed...

Successful suppression of dielectric relaxation inherent to high-k NAND from both architecture and material points of view

High-k materials, such as HfO<inf>2</inf> and Al<inf>2</inf>O<inf>3</inf>, are known to have dielectric relaxation effect (i.e. slow polarization) [1][2]. It is reported for the first time in this work that Al<inf>2</inf>O<inf>3</inf>, used as a blocking layer of MANOS NAND flash memory cells, causes modulation of channel current through its dielectric relaxation, resulting in severe transient threshold voltage shift as much as ∼ 0.8V. This V<inf>th</inf> drift cannot be controlled by bit-by-bit verify method, and will severely deteriorate multi-level functionality of NAND flash memory cells. In this work we propose two solutions for this issue. The first one is to give appropriate pre-bias to the word lines of a NAND string before a reading pulse sequence so that the V<inf>th</inf> drift due to dielectric relaxation can be compensated. The second one is to implement an Al<inf>2</inf>O<inf>3</inf>/SiO<inf>2</inf>/Al<inf>2</inf>O<inf>3</inf> (AOA) stacked blocking layer (Fig.1(b)) instead of an Al<inf>2</inf>O<inf>3</inf> single layer (Fig.1(a)). With these solutions, the transient V<inf>th</inf> drift due to dielectric relaxation can be eliminated entirely.

Direct Measurement of Back-Tunneling Current during Program/Erase Operation of Metal?Oxide?Nitride?Oxide?Semiconductor Memories and Its Dependence on Gate Work Function

In this study, we have established a novel scheme to extract the back-tunneling current from the transient characteristics of a metal–oxide–nitride–oxide–semiconductor (MONOS) memory capacitor during programming or erasing. Using a charge centroid extraction method, the separation of trapping current, leakage current and back-tunneling current was successfully accomplished. By studying the gate work function dependence of injected current, it was found that the leakage current due to electron injection from the Si substrate is the dominant component during deep programming and that the back-tunneling current due to electron injection from the gate electrode is the predominant component of injected current during deep erasing.

Suppression of silicidation in ZrO2/SiO2/Si structure by helium annealing

Suppression of silicidation in ZrO2/SiO2/Si structure by high-temperature helium (He) gas annealing was demonstrated. Comparison of ultrahigh vacuum, 1 Torr N2 and He annealing with controlled oxygen partial pressure (PO2) at 920 °C revealed that the optimal PO2 range in He at which the thermal stability of the layered structure can be achieved is over one order wider than that in N2. This result suggests that He gas physically obstructs SiO removal through the quenching of atomic vibration and the occupation of SiO diffusion path in the ZrO2/SiO2 layer, thus impeding the contact of ZrO2, SiO, and Si effectively, which is the trigger of silicidation. Moreover, rapid thermal He annealing is found to be the most effective means of suppressing transition of interface structure.