Jun Fujiki

Hybrid CMOS/BEOL-NEMS technology for ultra-low-power IC applications

Three-dimensional (3-D) nano-electro-mechanical (NEM) switches (relays) are proposed to reduce the die area and power consumption of digital logic and memory circuits.

Microelectromechanical Relay and Logic Circuit Design for Zero Crowbar Current

A compact microelectromechanical (MEM) switch design and associated family of logic gates, memory cells, and other basic very-large-scale integration (VLSI) digital circuit sub blocks are proposed to ensure zero crowbar current in addition to zero leakage current while minimizing mechanical delay. The circuit design methodology introduced in this paper also provides for lower device count and hence lower operating power consumption. A prototype of the MEM switch design is demonstrated.

Successful suppression of dielectric relaxation inherent to high-k NAND from both architecture and material points of view

High-k materials, such as HfO<inf>2</inf> and Al<inf>2</inf>O<inf>3</inf>, are known to have dielectric relaxation effect (i.e. slow polarization) [1][2]. It is reported for the first time in this work that Al<inf>2</inf>O<inf>3</inf>, used as a blocking layer of MANOS NAND flash memory cells, causes modulation of channel current through its dielectric relaxation, resulting in severe transient threshold voltage shift as much as ∼ 0.8V. This V<inf>th</inf> drift cannot be controlled by bit-by-bit verify method, and will severely deteriorate multi-level functionality of NAND flash memory cells. In this work we propose two solutions for this issue. The first one is to give appropriate pre-bias to the word lines of a NAND string before a reading pulse sequence so that the V<inf>th</inf> drift due to dielectric relaxation can be compensated. The second one is to implement an Al<inf>2</inf>O<inf>3</inf>/SiO<inf>2</inf>/Al<inf>2</inf>O<inf>3</inf> (AOA) stacked blocking layer (Fig.1(b)) instead of an Al<inf>2</inf>O<inf>3</inf> single layer (Fig.1(a)). With these solutions, the transient V<inf>th</inf> drift due to dielectric relaxation can be eliminated entirely.

Dynamics of the Charge Centroid in Metal–Oxide–Nitride–Oxide–Silicon Memory Cells during Avalanche Injection and Fowler–Nordheim Injection Based on Incremental-Step-Pulse Programming

In this study we have carried out a precise analysis on transient charge centroid dynamics during the programming of metal–oxide–nitride–oxide–silicon (MONOS) memory cells. Using the incremental-step-pulse programming (ISPP) scheme, the charge centroid is exactly extracted during the programming. Furthermore, avalanche injection enables low-field carrier injection, making it easy to identify the accessible trap sites in the charge trap layer. Avalanche injection is also used to study the field dependence of available traps. From this analysis, the charge centroid of MONOS memory is found to move from the tunnel layer/charge layer interface to the charge layer/block layer interface during low-field programming. In contrast, the location of the charge centroid is limited to the charge layer/block layer interface when the Fowler–Nordheim (FN) injection is used for programming at a high electric field. Furthermore, the low-electric-field programming achieves a high capture efficiency owing to a larger flatband shift in this programming than in high-electric-field programming. Therefore, low-electric-field programming is desired to increase the trap site availability and carrier capture efficiency.

NEM relay design for compact, ultra-low-power digital logic circuits

Since mechanical switches (relays) have zero off-state leakage and perfectly abrupt ON/OFF switching behavior, in principle they can be operated with a very small voltage swing and overcome the energy efficiency limit of CMOS technology. This paper discusses recent developments to address the remaining technical challenges for fully realizing the promise of ultra-low-power mechanical computing.

Transition of erase mechanism for MONOS memory depending on SiN composition and its impact on cycling degradation

We clarify the origin of erase improvement in MONOS memories with Si-rich SiN layer, and investigate the impact of erase mechanism on cycling degradation. It is demonstrated that cycling degradation is uniquely determined by charges injected during erase operations irrespective of program/erase condition, number of program/erase cycling, or MONOS structure.

Direct Measurement of Back-Tunneling Current during Program/Erase Operation of Metal?Oxide?Nitride?Oxide?Semiconductor Memories and Its Dependence on Gate Work Function

In this study, we have established a novel scheme to extract the back-tunneling current from the transient characteristics of a metal–oxide–nitride–oxide–semiconductor (MONOS) memory capacitor during programming or erasing. Using a charge centroid extraction method, the separation of trapping current, leakage current and back-tunneling current was successfully accomplished. By studying the gate work function dependence of injected current, it was found that the leakage current due to electron injection from the Si substrate is the dominant component during deep programming and that the back-tunneling current due to electron injection from the gate electrode is the predominant component of injected current during deep erasing.

A New Method to Extract the Charge Centroid in the Program Operation of MONOS memories

Introduction MONOS type device is a candidate to replace conventional floating gate (FG) non-volatile memory devices because of its low program/erase (P/E) voltage and reduced cell-to-cell interference effect. Instead of poly silicon FG, silicon nitride (SiN), which has discrete traps distributed in the thickness direction, is employed as a charge trap layer of MONOS devices. Then, the information about vertical position of trapped charge is important to understand the trapping properties of SiN layer and to improve the performance and reliability of MONOS devices. Although several techniques for charge centroid evaluation are proposed [1-4], some of these techniques require special device structures such as MONOS with lightly doped poly Si gate [3] or very thick (~50nm) SiN layer [4]. Three-level pulse method [1] is a relatively simple technique among the existing methods in the sense that it uses an ordinary MONOS structure, but this method demands a measurement of P/E characteristics in advance. Here, we present a new simple measurement technique to extract the charge centroid in the nitride layer during the program operation that improves the three-level pulse method.

Direct Measurement of Back-Tunneling Current during Program/Erase Operation of MONOS Memories and Its Dependence on Gate Work Function

Introduction MONOS memory is one of the candidates to replace floating gate (FG) non-volatile memory with its simple structure and less cell-to-cell interference [1]. Although multi-level cell operation is expected in MONOS memories to realize high density data storage, leakage current and back-tunneling current during program/erase (P/E) operation bring about Vth saturation [2] and narrow Vth window. Besides, it is known that penetration current severely degrades device reliability [3]. Thus, it is necessary to analyze current components of MONOS devices. Based on the charge-centroid extraction method [4][5], we have developed an analysis method which enables extracting back tunneling current component. In this paper, gate work function dependence of back-tunneling current during P/E operation is discussed to confirm the validity of our analysis scheme.

Dynamics of the Charge Centroid in MONOS Memory Cells during Avalanche Injection and FN Injection Based on Incremental-Step-Pulse-Programming

Introduction Although MONOS type memory cells are intensively studied thanks to their applicability to 3-dimensionally integrated structure such as BiCS flash memory [1], the future memory generations are facing performance and reliability issues. To solve these issues, it is important to clarify the transient carrier capture dynamics and evaluate key parameters such as the charge centroid [2]. Further multibit requirement imposes wider programming window on memory cells, and the window enhancement has been studied in terms of trap density and distribution by means of avalanche injection method [3]. However, the applied electric fields across the memory cell during avalanche injection and FN injection (normally used in NAND flash memory) are substantially different. So we have to know whether the extracted traps in avalanche injection are available on NAND application at a high field. In this paper we clarify the dynamics and electric field dependence of the charge centroid for the first time. As a prerequisite to extract the charge centroid, capture efficiency of 100% should be verified [2]. For this purpose, we make use of an indicator derived from the incremental step pulse programming (ISPP), and found that the extracted charge centroid moves toward the charge layer / block layer interface during avalanche injection. In addition, the location of available traps shifts as a function of electric field, continuously from avalanche injection to FN injection.