Kouichi Saitou

Development of a novel Wafer-Level-Packaging technology using laminating process

We have been developing a novel Wafer Level Packaging technology which has a possibility of lowering WLP cost drastically by applying some Jisso techniques to WLP manufacturing processes. In short, our idea is laminating a Cu wafer having Cu bumps to a Si wafer in which LSIs are formed with a nonconductive thermosetting resin. The process flow of the developed WLP technology is as follows; 1. Cu bump formation by wet etching of a Cu wafer (same shape with a Si wafer) 2. Ni/Au plating both on top of the Cu bumps and Al electrodes on Si wafer 3. NCF (Non Conductive Film) laminating to a bump side of the Cu wafer 4. Laminating (thermo compression bonding) of Cu and Si wafer after alignment 5. Re-distribution layer (RDL) formation by wet etching of the Cu wafer laminated with the Si wafer 6. PSR laminating, solder ball mounting, and dicing

Fine pitch connection and thermal stress analysis of a novel Wafer Level Packaging technology using laminating process

We have been developing a novel Wafer Level Packaging technology which has a possibility of lowering WLP cost drastically by applying some JISSO techniques to WLP manufacturing processes [1]. In short, our idea is laminating a Cu wafer having Cu bumps to a Si wafer in which LSIs are formed with a nonconductive thermosetting resin. The process flow of the novel WLP technology is as follows; 1. Cu bump formation by wet etching of a Cu wafer 2. Ni/Au plating both on top of the Cu bumps and Al electrodes on Si wafer 3. NCF (Non Conductive Film) laminating to a bump side of the Cu wafer 4. Laminating (thermo compression bonding) of Cu and Si wafer after alignment 5. Re-distribution wiring formation by wet etching of the Cu wafer 6. PSR laminating, solder ball mounting, and dicing In this work, fine pitch connection (less than 100um) for the novel WLP technology has been investigated. To achieve it, there are two major issues; Cu thickness before redistribution wiring formation, and misalignment between Cu bumps and LSI electrodes. As for the Cu thickness, less than 20um is required for the fine pitch re-distribution formation, and should be more than 40um at the laminating process because of handling property (easy to convey, avoiding wrinkle or scar). To solve the mismatch of the thickness, we established a process flow in which 40–50um thick Cu is laminated with Si, Cu is wet etched down to 10–20um, then re-distribution is formed. To reduce the misalignment, we made a thermal expansion model and extracted an equation which determines an optimum offset value for any laminating conditions. By using the equation, misalignment within a wafer was reduced to less than 15um. Applying the above, good electrical connection was confirmed with fine pitch of less than 100um (60–80um). In addition, thermal stress analysis was applied to a structure of a WLP mounted on a PCB. As a result of the analysis, cumulative equivalent inelastic strain of solder ball, which connects the WLP and the PCB electrode, during temperature cycling test of our novel WLP structure was less than that of the conventional Cu post type WLP. It shows that the novel WLP structure has good stress relaxation property and board level reliability.