Mayumi Nakasato

Development of a novel Wafer-Level-Packaging technology using laminating process

We have been developing a novel Wafer Level Packaging technology which has a possibility of lowering WLP cost drastically by applying some Jisso techniques to WLP manufacturing processes. In short, our idea is laminating a Cu wafer having Cu bumps to a Si wafer in which LSIs are formed with a nonconductive thermosetting resin. The process flow of the developed WLP technology is as follows; 1. Cu bump formation by wet etching of a Cu wafer (same shape with a Si wafer) 2. Ni/Au plating both on top of the Cu bumps and Al electrodes on Si wafer 3. NCF (Non Conductive Film) laminating to a bump side of the Cu wafer 4. Laminating (thermo compression bonding) of Cu and Si wafer after alignment 5. Re-distribution layer (RDL) formation by wet etching of the Cu wafer laminated with the Si wafer 6. PSR laminating, solder ball mounting, and dicing

Fine pitch connection and thermal stress analysis of a novel Wafer Level Packaging technology using laminating process

We have been developing a novel Wafer Level Packaging technology which has a possibility of lowering WLP cost drastically by applying some JISSO techniques to WLP manufacturing processes [1]. In short, our idea is laminating a Cu wafer having Cu bumps to a Si wafer in which LSIs are formed with a nonconductive thermosetting resin. The process flow of the novel WLP technology is as follows; 1. Cu bump formation by wet etching of a Cu wafer 2. Ni/Au plating both on top of the Cu bumps and Al electrodes on Si wafer 3. NCF (Non Conductive Film) laminating to a bump side of the Cu wafer 4. Laminating (thermo compression bonding) of Cu and Si wafer after alignment 5. Re-distribution wiring formation by wet etching of the Cu wafer 6. PSR laminating, solder ball mounting, and dicing In this work, fine pitch connection (less than 100um) for the novel WLP technology has been investigated. To achieve it, there are two major issues; Cu thickness before redistribution wiring formation, and misalignment between Cu bumps and LSI electrodes. As for the Cu thickness, less than 20um is required for the fine pitch re-distribution formation, and should be more than 40um at the laminating process because of handling property (easy to convey, avoiding wrinkle or scar). To solve the mismatch of the thickness, we established a process flow in which 40–50um thick Cu is laminated with Si, Cu is wet etched down to 10–20um, then re-distribution is formed. To reduce the misalignment, we made a thermal expansion model and extracted an equation which determines an optimum offset value for any laminating conditions. By using the equation, misalignment within a wafer was reduced to less than 15um. Applying the above, good electrical connection was confirmed with fine pitch of less than 100um (60–80um). In addition, thermal stress analysis was applied to a structure of a WLP mounted on a PCB. As a result of the analysis, cumulative equivalent inelastic strain of solder ball, which connects the WLP and the PCB electrode, during temperature cycling test of our novel WLP structure was less than that of the conventional Cu post type WLP. It shows that the novel WLP structure has good stress relaxation property and board level reliability.

Development of Material and Processing Technology for High Thermal Conductive Multilayer Module

We have developed a multilayer substrate that is formed from a high thermal conductive resin including ceramic fillers at high density in order to realize a module that is more miniaturized and has lower thermal resistance. First, we realized a resin with a very high filler filling rate of 75% by mixing two kinds of spherical fillers different in particle size. The thermal conductivity of the insulation resin films we developed is 4.4 W/mK. And we were able to make resin films with a thickness from 35 mum-120 mum. Additionally, with the improvement of adhesion between Cu and resin affected by control of the resin fluidity and filler diameter, a high thermal conductive multilayer substrate could be realized. The reliability of the high thermal conductive multilayer substrate formed from the developed resin was then investigated. Even after 1000 cycles of HC test (heat cycle test: 233 K-398 K, 30 minutes at each temperature), the resistance of the daisy chain pattern did not change. The THB test results (temperature, humidity, and bias test: 358 K, 85% RH, 50 V), showed that an insulation layer of more than 60 mum thickness gives enough dielectric reliability. Finally, we made a high voltage (350 V) drive inverter power supply circuit module for automobile applications including the high thermal conductive multilayer substrate we developed. Applying a multilayer substrate enabled the inverter module to be downsized to 85% of the one with a conventional monolayer substrate. Further, the thermal resistance of the miniaturized module was the same as the conventional module. In addition, the results of HC test and THB test indicated that the reliability of the developed module is sufficient for automobile applications.