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Dive into the research topics where Yoshio Okayama is active.

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Featured researches published by Yoshio Okayama.


electronic components and technology conference | 2009

Development of a novel Wafer-Level-Packaging technology using laminating process

Yoshio Okayama; Yasuyuki Yanase; Kouichi Saitou; Hajime Kobayashi; Mayumi Nakasato; Tetsuya Yamamoto; Ryosuke Usui; Yasunori Inoue

We have been developing a novel Wafer Level Packaging technology which has a possibility of lowering WLP cost drastically by applying some Jisso techniques to WLP manufacturing processes. In short, our idea is laminating a Cu wafer having Cu bumps to a Si wafer in which LSIs are formed with a nonconductive thermosetting resin. The process flow of the developed WLP technology is as follows; 1. Cu bump formation by wet etching of a Cu wafer (same shape with a Si wafer) 2. Ni/Au plating both on top of the Cu bumps and Al electrodes on Si wafer 3. NCF (Non Conductive Film) laminating to a bump side of the Cu wafer 4. Laminating (thermo compression bonding) of Cu and Si wafer after alignment 5. Re-distribution layer (RDL) formation by wet etching of the Cu wafer laminated with the Si wafer 6. PSR laminating, solder ball mounting, and dicing


electronic components and technology conference | 2010

Fine pitch connection and thermal stress analysis of a novel Wafer Level Packaging technology using laminating process

Yoshio Okayama; Mayumi Nakasato; Kouichi Saitou; Yasuyuki Yanase; Hajime Kobayashi; Tetsuya Yamamoto; Ryosuke Usui; Yasunori Inoue

We have been developing a novel Wafer Level Packaging technology which has a possibility of lowering WLP cost drastically by applying some JISSO techniques to WLP manufacturing processes [1]. In short, our idea is laminating a Cu wafer having Cu bumps to a Si wafer in which LSIs are formed with a nonconductive thermosetting resin. The process flow of the novel WLP technology is as follows; 1. Cu bump formation by wet etching of a Cu wafer 2. Ni/Au plating both on top of the Cu bumps and Al electrodes on Si wafer 3. NCF (Non Conductive Film) laminating to a bump side of the Cu wafer 4. Laminating (thermo compression bonding) of Cu and Si wafer after alignment 5. Re-distribution wiring formation by wet etching of the Cu wafer 6. PSR laminating, solder ball mounting, and dicing In this work, fine pitch connection (less than 100um) for the novel WLP technology has been investigated. To achieve it, there are two major issues; Cu thickness before redistribution wiring formation, and misalignment between Cu bumps and LSI electrodes. As for the Cu thickness, less than 20um is required for the fine pitch re-distribution formation, and should be more than 40um at the laminating process because of handling property (easy to convey, avoiding wrinkle or scar). To solve the mismatch of the thickness, we established a process flow in which 40–50um thick Cu is laminated with Si, Cu is wet etched down to 10–20um, then re-distribution is formed. To reduce the misalignment, we made a thermal expansion model and extracted an equation which determines an optimum offset value for any laminating conditions. By using the equation, misalignment within a wafer was reduced to less than 15um. Applying the above, good electrical connection was confirmed with fine pitch of less than 100um (60–80um). In addition, thermal stress analysis was applied to a structure of a WLP mounted on a PCB. As a result of the analysis, cumulative equivalent inelastic strain of solder ball, which connects the WLP and the PCB electrode, during temperature cycling test of our novel WLP structure was less than that of the conventional Cu post type WLP. It shows that the novel WLP structure has good stress relaxation property and board level reliability.


electronic components and technology conference | 2004

Process integration of 3D chip stack with vertical interconnection

Kenji Takahashi; Y. Taguchi; Manabu Tomisaka; Hitoshi Yonemura; Masataka Hoshino; M. Ueno; Y. Egawa; Yoshihiko Nemoto; Yasuhiro Yamaji; Hiroshi Terao; Mitsuo Umemoto; K. Kameyama; A. Suzuki; Yoshio Okayama; Toshihiro Yonezawa; K. Kondo


Archive | 2002

Semiconductor device and method for manufacturing thereof

Tomio Yamashita; Yoshio Okayama


Archive | 2008

SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE, AND PORTABLE DEVICE

Yasuyuki Yanase; Yoshio Okayama; Ryosuke Usui


Archive | 2008

SUBSTRATE FOR MOUNTING DEVICE AND METHOD FOR PRODUCING THE SAME, SEMICONDUCTOR MODULE AND METHOD FOR PRODUCING THE SAME, AND PORTABLE APPARATUS PROVIDED WITH THE SAME

Kouichi Saitou; Yoshio Okayama; Yoh Takano; Mayumi Nakasato


Archive | 2007

SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING THE SEMICONDUCTOR MODULE AND PORTABLE DEVICE CARRYING THE SAME

Yoshio Okayama


Archive | 2010

SEMICONDUCTOR MODULE, METHOD OF MANUFACTURING SEMICONDUCTOR MODULE, AND MOBILE DEVICE

Yasuyuki Yanase; Yoshio Okayama; Kiyoshi Shibata; Yasunori Inoue; Hideki Mizuhara; Ryosuke Usui; Tetsuya Yamamoto; Masurao Yoshii


Archive | 2010

Semiconductor laser device, optical pickup device and semiconductor device

Yoshio Okayama; Yasunori Inoue; Takenori Goto; Kazushi Mori; Yuuki Ota; Naoteru Matsubara


Archive | 1997

Fabrication method of semiconductor device and abrasive liquid used therein

Yasunori Inoue; Yoshio Okayama

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Akira Suzuki

National Institute of Advanced Industrial Science and Technology

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