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Dive into the research topics where Kouji Ichikawa is active.

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Featured researches published by Kouji Ichikawa.


international symposium on electromagnetic compatibility | 2006

Simulation of integrated circuit immunity with LECCS model

Kouji Ichikawa; Masashi Inagaki; Yukihiko Sakurai; Isao Iwase; Makoto Nagata; Osami Wada

We have been developing an LSI model for EMC simulation in electronic control units. EMI simulations have been applied to some units using an LSI EMI model. These models have been called the LECCS Model and ICEM Model, but there are few examples of EMS simulation in printed circuit boards. Therefore , we studied the LSI EMS model and attempted to perform an EMS simulation of a printed circuit board. The LSI was tested through the DPI method (IEC61967-4). The EMS in this test system was analyzed, and the usefulness of this method of analysis was confirmed. The analysis was also applied to a product


IEICE Transactions on Electronics | 2007

Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements

Kouji Ichikawa; Yuki Takahashi; Makoto Nagata

Power supply noise waveforms are acquired in a voltage domain by an on-chip monitor at resolutions of 0.3 ns/1.2 mV, in a digital test circuit consisting of 0.18-μm CMOS standard logic cells. Concurrently, magnetic field variation on a printed circuit board (PCB) due to power supply current of the test circuit is measured by an off-chip magnetic probing technique. An equivalent circuit model that unifies on- and off-chip impedance network of the entire test setup for EMI analysis is used for calculating the on-chip voltage-mode power supply noise from the off-chip magnetic field measurements. We have confirmed excellent consistency in frequency components of power supply noises up to 300MHz among those derived by the on-chip direct sensing and the off-chip magnetic probing techniques. These results not only validate the state-of-the art EMI analysis methodology but also promise its connectivity with on-chip power supply integrity analysis at the integrated circuit level, for the first time in both technical fields.


european conference on circuit theory and design | 2013

An estimation method for the n port S parameters with n-1 port measurements

Noboru Maeda; Shinji Fukui; Kouji Ichikawa; Yukihiko Sakurai; Toshikazu Sekine; Yasuhiro Takahashi

An estimation method of the three-port S-parameters for reciprocal circuits is presented. In this method, several known loads are connected to two of the ports and reflection characteristic of the remaining port is measured. Therefore, there is no need to connect network analyzer to the ports which are connected to the known loads. S-parameters are obtained by solving a linear system equations and quadratic equations only. In addition, a method for determining the port voltages from the estimated S parameters is also described, Then applying this method to estimate the S-parameters of an immunity test system, validness of this method has been confirmed. The proposed method will be applied when there is no common ground between each ports.An estimation method of the n-port S-parameters for reciprocal circuits is presented. In this method, several known loads are connected to one port in turn and reflection and transmission characteristics among the remaining ports are measured. Therefore, there is no need to connect a network analyzer to the port that is connected to the known loads. S-parameters are obtained by solving a linear least-squares equation and a quadratic equation only. In addition, applying this method to estimate the S-parameters of an immunity test system, validness of this method is confirmed.


electrical design of advanced packaging and systems symposium | 2008

Modeling of microcontroller with multiple power supply pins for conducted EMI simulations

Kengo Iokibe; Ryota Higashi; Takahiro Tsuda; Kouji Ichikawa; Katsumi Nakamura; Yoshitaka Toyota; Ryuji Koga

An EMC macro-model of a 16-bit microcontroller with multiple-power-supply pins has been proposed for estimating the conducted EMI from a power-supply network. The macro-model, called the linear equivalent circuit and current sources (LECCS) model, is composed of multiple circuit blocks and multiple current sources corresponding to the composition of the chip circuits in the microcontroller, i.e., a current source for a circuit block. A current source statistically expresses the total RF current occurring in the corresponding circuit block. We confirmed that the proposed model could correctly estimate the RF power-supply currents under different decoupling conditions up to 300 MHz. We also found that a linear circuit of the regulator between the I/O and core circuit blocks could express the RF coupling between the two blocks.


international symposium on electromagnetic compatibility | 2006

EMI model improvement taking LSI package structure into consideration

Kouji Ichikawa; T. Unou; T. Tsuda; Y. Mabuchi; Makoto Nagata

An LSI EMI model comprising separate blocks with current sources within a microcomputer was used to analyze conducted emission noise in a power circuit of a product board, in order to examine the PCB power circuit system in an automotive electronic control unit (ECU). An LSIs EMI model has separate blocks for each current source and each linear circuit system. They were used to analyze conducted emission noise of a PCB power circuit system. The EMS model was also applied to PCB simulation. The attempt was made to improve the EMI model so as to achieve higher accuracy in the analysis, and its effectiveness was confirmed. The trend toward electronic control of devices in modern vehicles is advancing at a remarkable rate, as is the pace at which the capability of these devices is being improved. More shorter product development cycles are required to improve competitiveness. The cost of an ECU is also decreasing, the printed circuit boards used generally have fewer layers than regular consumer products; in most cases, they are single-sided or double-sided. The number of noise reduction or suppression components that can be used is also limited. In addition, there is a trend to shorter product development times. Prompt EMC performance of the ECU has a great impact on product development. The semiconductors (IC/LSI) supporting these systems also must have increasingly high EMC performance. EMC problems of ECUs are affected more and more by the EMC performance of these semiconductors. Key tasks in the system design for the assurance of EMC performance include the selection of semiconductors with low noise and high immunity, and the investigation of the installation method, for instance, the peripheral layout design of semiconductors on printed circuit boards. EMC performance of products must be considered from the initial design phase. To examine these issues, we are researching the LSI EMC- model for PCB simulation. Especially, a simulation is very important for investigation of the installing method. An LSI is assumed to be a noise source and an origin of system malfunction. Therefore, accuracy and diversity are necessary to analyze EMC mechanism of PCB.


international meeting for future of electron devices, kansai | 2012

Co-evaluation of power supply noise of CMOS microprocessor using on-board magnetic probing and on-chip waveform capturing techniques

Yuta Sasaki; Kumpei Yoshikawa; Makoto Nagata; Kouji Ichikawa

On-chip and on-board power noise measurements were performed on a 32-bit microprocessor core in a 90-nm CMOS technology. The on-chip voltage noise and on-board near-field magnetic field measurements are related to each other with a unified power delivery network that is formed by on-chip and on-board parasitic components. The significant importance of LSI chip-package-board co-simulation is also discussed from the measurement results.


IEICE Transactions on Electronics | 2008

Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation

Kouji Ichikawa; Yuki Takahashi; Yukihiko Sakurai; Takahiro Tsuda; Isao Iwase; Makoto Nagata

Impacts of electromagnetic (EM) interference (immunity) on operation of LSI circuits in a QFP-packaged and PCB-mounted environment are studied. EM power injection to a power-supply system leads to malfunction, where the power is translated into voltage bounces through combined on- and off- chip impedances, affecting power supply and ground, as well as signal nodes in a die, seen from on-chip waveform measurements. A lumped power-supply impedance model and the minimum amplitude of voltage bounce induced by EM power for malfunction, both of which can be derived from external measurements to a given packaged LSI, formulate an EM interference model that is helpful in the PCB design toward high immunity. The technique can be generally applied to systems-on-chip applications.


international symposium on electromagnetic compatibility | 2006

Novel design technique for reducing common-mode current on wire harness connected to ECUs

Yuichi Mabuchi; Atsushi Nakamura; T. Hayashi; Takanori Uno; Kouji Ichikawa; Hiroshi Mizuno; T. Matsui

A key parameter that controls common-mode cur- rent on the cable connected to electronic control units (ECUs) is investigated. Supply currents for the CPU on ECUs and parasitic inductance / capacitance of supply traces on printed circuit boards (PCBs) generate common-mode current on the cable. We found the amount of common-mode current can be reduced sensitively by adjusting the balance of parasitic inductance / capacitance. The new approach proposed in this paper allows minimizing the common-mode current and suppress the radiation less than the currently achievable level. This technique is proven experimentally with evaluation boards and the influence of these parameters on common-mode current is confirmed by our simulation technique. I. INTRODUCTION Nowadays, a driving speed of LSI is getting faster and it is equipped on electronic device denser than past one. According to these situations, electromagnetic radiation from electronic devices becomes larger and it gives harmful influence on electronic devices such as jamming of radio communication or miss action of its circuits. Especially in automobile, EMI/EMC becomes very serious problem because many electronic de- vices are equipped together with a radio in a car. The origin of electromagnetic radiation emitted from electronic device is voltage fluctuation and high frequency current that are exited when LIS is driving. These voltage fluctuation and high fre- quency current drive printed circuit boards (PCBs), their frame and cable attached to them as antennas and electromagnetic wave is radiated from them. At VHF (30∼300MHz) frequency


international meeting for future of electron devices, kansai | 2013

Power-noise measurements of small-scale inverter chains

Yuji Harada; Kumpei Yoshikawa; Noriyuki Miura; Makoto Nagata; Akitaka Murata; Syuji Agatsuma; Kouji Ichikawa

This paper presents the measurements of power noise (Vdd noise) waveforms of a 5-stage inverter chain, using on-chip noise monitor circuits (OCM). The fine resolution of 0.4 mV in voltage and 12.5 ps in timing are realized. The undesired voltage variation by signal buffers in I/O cells is carefully eliminated by three means; (i) isolation of power domains, (ii) subtraction of background noise waveforms, and (iii) averaging iteratively captured waveforms.


electrical design of advanced packaging and systems symposium | 2013

Mathematics of 2r-port S-parameter Estimation by the r-port measurements

Noboru Maeda; Shinji Fukui; Takashi Naoi; Kouji Ichikawa; Toshikazu Sekine; Yasuhiro Takahashi

An estimation method of the 2r-port S-parameters for reciprocal circuits is presented. In this method, several known loads are connected to r ports in turn and reflection and transmission characteristics among the remaining r ports are measured. Therefore, there is no need to connect a network analyzer to the ports that are connected to the known loads. S-parameters are obtained by solving several linear equations and quadratic equations only. In addition, applying this method to estimate the S-parameters of an circuit model of an enclosure mounting an IC chip, validness of this method is confirmed.

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Osamu Fujiwara

Nagoya Institute of Technology

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