Kumpei Yoshikawa

Evaluation of Thin Film Noise Suppressor Applied to Noise Emulator Chip Implemented in 65 nm CMOS Technology

This paper reports the shielding effect of soft magnetic film as a thin film noise suppressor applied to a test chip implemented in 65 nm seven metal CMOS technology. This test chip is equipped with a noise generator circuit. The 0.2-1- μm-thick magnetic films, which are integrated with polyimide substrates, are mounted onto the noise generator circuit in the test chip, and 2-μm-thick magnetic film is directly integrated to the passivation of the test chip. These films are deposited by RF magnetron spattering. The shield effect is evaluated by magnetic near-field measurement using planar shielded loop probe and 3-D full-wave electromagnetic field simulation. As a result, we successfully demonstrate a shield effect of 7.7 dB at a crock frequency of 200 MHz with 2-μ m-thick CoZrNb film. Furthermore, the result of the thickness dependence of the shielding effect revealed that a permeability-thickness product (μr × tm) of 1 950 μ m is required as the design target for obtaining 10 dB suppression.

Measurements of SRAM sensitivity against AC power noise with effects of device variation

SRAM exhibits the sensitivity of false operation against static and sinusoidal supply voltage variation. A measurement system combines direct radio frequency (RF) power injection, on-chip monitoring of voltage variation on power supply lines, and built-in self test of memory read/write operations. The bit error rate (BER) of an SRAM core exponentially increases when the lowest instantaneous voltage on the power supply line of SRAM cells during RF injection linearly decreases. Test dice on wafers at five different process corners in a 1.5 V 90 nm CMOS technology were tested. The minimum allowable voltage with BER of less than a single bit failure in average becomes smaller, thus more tolerant, when n-channel devices are at the slow corner in a conventional 6-transistor SRAM cell. The measurement technique enables to experimentally evaluate dynamic noise margin of SRAM cores in a given technology.

An on-chip waveform capturer for diagnosing off-chip power delivery

In-place diagnosis of off-chip power delivery resonance is demonstrated with on-chip waveform capturer and power delivery network (PDN) exciter that were prototyped in a 65 nm CMOS technology. Oscillatory waveforms are captured after the excitation of PDN, from which an LCR lumped equivalent circuit of PDN seen by on-chip circuits is algorithmically derived. The consistency of component values is confirmed among the demonstrated in-place diagnosis and full-wave analysis.

A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils

This paper presents a low-power and compact passive supply-resonance (SR) suppression filter. By using an on-chip waveform monitor, a power-delivery network (PDN) impedance including package, and board PDNs is in-situ analyzed to identify the SR frequency fSR. A notch filter which consists of coupled bonding-wire coils and an on-chip MOS capacitor bank is auto-tuned for the SR suppression. This passive filtering approach reduces the power loss to 1/5~1/10 and the static power to effectively zero as compared to an active SR suppression circuit [1]. The coupled bonding-wire coil enhances its self-inductance and hence shrinks the on-chip capacitor size for the layout-area saving. A 0.18μm CMOS test chip demonstrates SR suppression by >43% with only <;7% of power loss and <;0.034mm layout area penalty.

Co-evaluation of power supply noise of CMOS microprocessor using on-board magnetic probing and on-chip waveform capturing techniques

On-chip and on-board power noise measurements were performed on a 32-bit microprocessor core in a 90-nm CMOS technology. The on-chip voltage noise and on-board near-field magnetic field measurements are related to each other with a unified power delivery network that is formed by on-chip and on-board parasitic components. The significant importance of LSI chip-package-board co-simulation is also discussed from the measurement results.

Monitoring effective supply voltage within power rails of integrated circuits

An effective supply voltage monitor evaluates dynamic variation of (Vdd-Vss) within power rails of integrated circuits on a die. The monitor occupies an area of as small as 10.8 × 14.5 μm2 and is followed by backend digitizing circuits, both using 3.3 V thick oxide transistors in a 65 nm CMOS technology for covering all power domains from core circuits to peripheral I/O rings. A prototype demonstrates capturing of effective supply voltage waveforms in digital shift registers as well as in an array of analog comparators.

An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference

The direct radio frequency power injection (DPI) method was extended using on-chip voltage waveform monitoring and built-in self-test techniques. Static random access memory (SRAM) has been chosen as a demonstrator of the extended DPI method and exhibits a higher susceptibility against the lower interference frequency. This response is explained when we consider the time length of the threshold against how long the supply voltage stays lower than the specific voltage determined for a SRAM core. This voltage is also found to be comparable but slightly smaller than the static voltage margin of SRAM cells. In-place measurements using the extended DPI provide an in-depth understanding of the susceptibility and help us to enhance the immunity of VLSI circuits.

Power-noise measurements of small-scale inverter chains

This paper presents the measurements of power noise (Vdd noise) waveforms of a 5-stage inverter chain, using on-chip noise monitor circuits (OCM). The fine resolution of 0.4 mV in voltage and 12.5 ps in timing are realized. The undesired voltage variation by signal buffers in I/O cells is carefully eliminated by three means; (i) isolation of power domains, (ii) subtraction of background noise waveforms, and (iii) averaging iteratively captured waveforms.

Co-simulation of AC power noise of CMOS microprocessor using capacitor charging modeling

Power noise could decisively impact on the system performance of large-scale integration (LSI), with higher integration and lower power supply voltage. Power noise simulation becomes a key step in the design of LSI systems. This paper presents an original capacitor-charging model that expresses AC part of power consumption current and also demonstrates power noise simulation of a 32 bit microprocessor on a 90 nm CMOS test chip. On-chip power supply voltage and on-board power supply current variations are consistently given by both measurements and simulation.