Krishna Kumar Bhuwalka

Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering

In this paper, we look into the scaling issues of a vertical tunnel field-effect transistor (FET). The device, a gated p-i-n diode based on silicon, showed gate-controlled band-to-band tunneling from the heavily doped source to the intrinsic channel. An exponentially increasing input characteristics, perfect saturation in the output characteristics, and off-currents of the order of 1 fA//spl mu/m for sub-100-nm channel lengths were observed. Further, with a /spl delta/p/sup +/ SiGe layer at the p-source end, improvements in the device performance in terms of on-current, threshold voltage and subthreshold swing were shown, albeit trading off the off-currents which increase with Ge content x. We show here that the tunnel FET performance is nearly independent of channel length scaling L and with /spl delta/p/sup +/ SiGe layer, scaling t/sub ox/ is not critical to tunnel FET scaling. Further, with gate workfunction engineering, the tunnel FET can be tuned to achieve a high on-current as well as very low off-currents. Due to the perfect saturation in the output characteristics, the device looks good for sub-100-nm low-power analog devices.

A simulation approach to optimize the electrical parameters of a vertical tunnel FET

Using two-dimensional device simulations, the electrical parameters of gated tunnel field-effect transistor (FET) are optimized with a SiGe delta doped layer in the source region. In order to prove the validity of the simulation models we compare simulation results with the experimentally realized tunnel FET on silicon and show that it gives a good match. It is shown that the incorporation of pseudomorphic strained-Si/sub 1-x/Ge/sub x/ layers leads to a significant performance increase. Furthermore, it becomes evident that the improvements are not a direct consequence of bandgap lowering but rather an indirect consequence of tunnel barrier width lowering. This leads to an asymmetry in the n- and the p-channel performance.

P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths

Experimental results of p-channel silicon vertical tunnel field-effect transistors down to sub-50 nm channel length are shown. As predicted by two-dimensional simulations, we show that the device on-current is nearly independent of channel length scaling. As the drain current is determined by electrons tunneling from the valence band to the conduction band, we show that mobility does not play any role in determining the device characteristics. Low temperature measurements reveal weak positive temperature coefficient in the transfer characteristics due to the dependence of bandgap on temperature. However, as expected for the silicon devices, low on-current is observed. Thus, we propose a lateral tunnel FET on SiGe-on-insulator with high on-currents and symmetric performance in n-channel as well as p-channel operating modes.

Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High-

The tunnel field-effect transistor (tunnel FET) is a promising candidate for future CMOS technology. Its device characteristics have been subject to a variety of experimental and theoretical studies. In this paper, we evaluate the influence of using a high-kappa gate dielectric in the tunnel FET compared to a standard silicon oxide with same equivalent oxide thickness, which exhibits a quite different behavior compared to a conventional MOSFET due to its totally different working principle. It turns out that the fringing field effect, while deteriorating conventional MOSFET characteristics, leads to a much higher on-current comparable with actual conventional MOSFETs, a subthreshold slope of the tunnel FET lower than the theoretical limit for conventional MOSFETs, and a massive improved inverter delay, underlining its prospect for future applications. This leads to the conclusion that high-kappa materials with permittivities > 30 can advantageously be used in CMOS technology, giving rise to further technological development.

\kappa

This letter presents experimental results and explanations on the reduced degradation caused by hot carriers of the vertical impact-ionization MOSFET (I-MOS) compared to the lateral device. The control and reduction of hot-carrier damage in an impact-ionization device is an important issue to make it a serious alternative for the conventional MOSFET to overcome the kT/q limit for the subthreshold slope of 60 mV/dec at room temperature. The vertical I-MOS shows an excellent subthreshold slope of about 13 mV/dec combined with a suppression of hot-carrier damage for the most part for many tens of thousands of switching cycles. We will explain the effects, which lead to this stability and validate it by measurements and simulations

Gate Dielectrics

In this work we explore for the first time, the design space for n-channel T-FETs with gate lengths below 22 nm using extensive device simulations. We show that the heterojunction tunnel-FET can satisfy ITRS requirements for HP and LSTP can be achieved using a SiGe-source device by an optimum choice of gate dielectric thickness and Ge fraction in Si1-gammaGegamma.

Improved Reliability by Reduction of Hot-Electron Damage in the Vertical Impact-Ionization MOSFET (I-MOS)

The performance of a n-channel vertical tunnel field-effect transistor is shown to improve significantly by bandgap engineering at the tunneling junction. The bandgap modulation is achieved by inserting a heavily doped 3 nm delta SiGe layer at the p-source end. Since the bandgap at the tunneling junction determines the tunneling barrier height, having a SiGe delta layer results in lowering it. Thereby, increasing the tunneling probability under similar bias conditions. We show that controlling the Ge mole fraction, x, in SiGe, gives an additional parameter for control of device performance. Device on-current, I/sub on/, and threshold voltage, V/sub T/, are seen to improve considerably. However, as the device is scaled down, the tunneling probability increases significantly even for V/sub GS/=0 V as x is increased. Thereby, leading to large increase in tunneling leakage current. Optimization of the device performance can then be done by appropriate choice of x with gate oxide thickness, t/sub ox/, according to technology requirements.