Georgios Vellianitis

Germanium-based transistors for future high performance and low power logic applications

High mobility channel materials could replace strained Si to enhance speed performance and/or reduce power consumption in future transistors. Ge has the highest hole mobility among common elemental and compound semiconductors, and an electron mobility that is two times larger than that of Si. Ge is thus a promising channel material for future CMOS (Fig. 1). Key challenges include cost-effective integration of Ge on Si in a manufacturable process, formation of high-quality gate stack on Ge for n- and p-FETs at aggressively scaled EOTs that deliver high channel mobilities, and leakage issues related to its small bandgap. In this paper, we discuss recent research progress in advancing Ge-based transistor technologies. Integration of Ge on Si substrate to enable fabrication of high performance devices and formation of high-quality gate stack for Ge FETs (particularly for n-FETs) will be discussed. We also explore opportunities to boost the mobility of Ge, e.g. by incorporating Sn in Ge to form Ge1-xSnx. Furthermore, by raising the Sn composition, the band gap EG of Ge1-xSnx becomes smaller and transits from indirect to direct, making Ge1-xSnx a promising material for tunneling transistors.

Germanium n-Channel Planar FET and FinFET: Gate-Stack and Contact Optimization

We demonstrate Ge enhancement-mode nMOS FinFETs fabricated on 300-mm Si wafers, incorporating an optimized gate-stack (interface trap density D_it below 2 × 10¹¹ eV^-1 · cm^-2), n⁺-doping (active doping concentration Nact exceeding 1 × 10²⁰ cm^-3), and metallization (contact resistivity Pc below 2 × 10^-7 Ω · cm²) modules. A new circular transmission line Pc extraction model that captures the parasitic metal resistance is proposed. At a supply voltage VDD of 0.5 V, 40-nm-gate-length FinFET devices achieved an ON-performance ION of 50 μA/μm at an OFF-state current IOFF of 100 nA/μm, a subthreshold swing S_sat of 124 mV/decade, and a peak transconductance g_m of 310 μS/μm. The same gate-stack and contacts were deployed on planar devices for comparison. Both FinFET and planar devices in this paper achieved the highest reported g_m/S_sat at VDD = 0.5 V to date and the shortest gate lengths for Ge nMOS enhancement-mode transistors.

Multi-V T engineering in highly scaled CMOS bulk and FinFET devices through Ion Implantation into the metal gate stack featuring a 1.0nm EOT high-K oxide

We demonstrate multi-VT engineering on both CMOS bulk and FinFET devices through As implantation into a 1.0nm EOT TiN/high-K gate stack within a single metal single dielectric approach. We determine a As implantation process window enabling VT tuning without any device degradation. It is shown that this approach is suitable for multi-VT engineering with aggressively scaled dielectrics and, particularly, for fully depleted 3D device architectures.

Characteristics and Integration Challenges of FinFET-based Devices for (Sub-)22nm Technology Nodes Circuit Applications

for (Sub-)22nm Technology Nodes Circuit Applications A. Veloso, M. J. H. van Dal, N. Collaert, A. De Keersgieter, L. Witters, R. Rooyackers, A. Redolfi, S. Brus, R. Duffy, B. J. Pawlak, G. Vellianitis, B. Duriez, T. Mérelle, P. P. Absil, S. Biesemans, M. Jurczak, T. Hoffmann, and R. J. P. Lander IMEC, NXP-TSMC Research Center, Kapeldreef 75, B-3001 Leuven, Belgium Tel.: +32-16-28 17 28, Fax: +32-16-28 17 06, Email: Anabela.Veloso@imec.be