Gerben Doornbos

Germanium n-Channel Planar FET and FinFET: Gate-Stack and Contact Optimization

We demonstrate Ge enhancement-mode nMOS FinFETs fabricated on 300-mm Si wafers, incorporating an optimized gate-stack (interface trap density D_it below 2 × 10¹¹ eV^-1 · cm^-2), n⁺-doping (active doping concentration Nact exceeding 1 × 10²⁰ cm^-3), and metallization (contact resistivity Pc below 2 × 10^-7 Ω · cm²) modules. A new circular transmission line Pc extraction model that captures the parasitic metal resistance is proposed. At a supply voltage VDD of 0.5 V, 40-nm-gate-length FinFET devices achieved an ON-performance ION of 50 μA/μm at an OFF-state current IOFF of 100 nA/μm, a subthreshold swing S_sat of 124 mV/decade, and a peak transconductance g_m of 310 μS/μm. The same gate-stack and contacts were deployed on planar devices for comparison. Both FinFET and planar devices in this paper achieved the highest reported g_m/S_sat at VDD = 0.5 V to date and the shortest gate lengths for Ge nMOS enhancement-mode transistors.