Krishnakumar Sundaresan

Process and temperature compensation in a 7-MHz CMOS clock oscillator

This paper reports on the design and characterization of a process, temperature and supply compensation technique for a 7-MHz clock oscillator in a 0.25-/spl mu/m, two-poly five-metal (2P5M) CMOS process. Measurements made across a temperature range of -40/spl deg/C to 125/spl deg/C and 94 samples collected over four fabrication runs indicate a worst case combined variation of /spl plusmn/2.6% (with process, temperature and supply). No trimming was performed on any of these samples. The oscillation frequencies of 95% of the samples were found to fall within /spl plusmn/0.5% of the mean frequency and the standard deviation was 9.3 kHz. The variation of frequency with power supply was /spl plusmn/0.31% for a supply voltage range of 2.4-2.75 V. The clock generator is based on a three-stage differential ring oscillator. The variation of the frequency of the oscillator with temperature and process has been discussed and an adaptive biasing scheme incorporating a unique combination of a process corner sensing scheme and a temperature compensating network is developed. The biasing circuit changes the control voltage of the differential ring oscillator to maintain a constant frequency. A comparator included at the output stage ensures rail-to-rail swing. The oscillator is intended to serve as a start-up clock for micro-controller applications.

Electronically Temperature Compensated Silicon Bulk Acoustic Resonator Reference Oscillators

The paper describes the design and implementation of an electronically temperature compensated reference oscillator based on capacitive silicon micromechanical resonators. The design of a 5.5-MHz silicon bulk acoustic resonator has been optimized to offer high quality factor (> 100 000) while maintaining tunability in excess of 3000 ppm for fine-tuning and temperature compensation. Oscillations are sustained with a CMOS amplifier. When interfaced with the temperature compensating bias circuit, the oscillator exhibits a frequency drift of 39 ppm over 100degC as compared to an uncompensated frequency drift of 2830 ppm over the same range. The sustaining amplifier and compensation circuitry were fabricated in a 2P3M 0.6-mum CMOS process.

Temperature Compensated IBAR Reference Oscillators

This work presents a two-chip automatically temperature-compensated micromechanical IBAR reference oscillator with a temperature drift of 39ppm over 100 ° C. Temperature compensation is provided by a parabolic VPcorrection scheme and provides 10X improvement over previously reported results. Tunable 6MHz, 10MHz, and 20MHz resonators were characterized with 2000– 4500ppm tuning and Q up to 119000. Motional impedances as low as 218Ω were extracted from measurement data with VP= 18V. The interface IC for temperature compensation and oscillation consumes only 1.9mW. Measurements also show that temperature compensation of a 10MHz resonator with 65nm gaps is possible with less than 5V.

Micromechanical IBARs: Tunable High-

This paper presents a unique capacitive micromechanical resonator and oscillator architecture for temperature-compensated frequency references. The I-shaped bulk acoustic resonator (IBAR) is designed to have excellent electrical tunability for temperature compensation (TC) and dynamic frequency control. High quality factor and low motional resistance are also achieved. The applicable range of frequencies is 1-30 MHz, in which quality factors exceeding 100 000 have been measured. Resonator metrics, including the electrostatic tuning coefficient, normalized dynamic stiffness, and relative dynamic compliance, are introduced. A small-signal resistance in the resonator is reported and explained. This unexpected resistance is beneficial for oscillator functionality over a large temperature range. The interface IC, inclusive of all blocks for sustaining oscillations and TC, is also presented. A two-chip 6-MHz oscillator with a temperature stability of 39 ppm over 100°C is demonstrated. The interface IC consumes 1.9 mW.

Q

The paper presents a temperature compensated 100MHz reference oscillator based on a capacitive silicon bulk acoustic wave (BAW) resonator interfaced with a CMOS amplifier. The resonator is optimized for high quality factor (92000) and low impedance. The CMOS IC comprises of a transimpedance amplifier to sustain oscillations and an oven control mechanism for temperature control. A phase noise floor of -136dBc/Hz was measured for the oscillator and the temperature drift of frequency was measured to be 56ppm over 100degC

Resonators for Temperature-Compensated Reference Oscillators

A new capacitive micromechanical resonator design optimized for high Q, low motional impedance, and large tuning range is presented. The I/sup 2/ resonator was fabricated using a conservative, by present standards, HARPSS-on-SOI process, and demonstrated quality factors up to 57000 in vacuum. From the designed resonators between 3MHz and 6MHz, the lowest measured impedance is 24k/spl Omega/ and the largest electrostatic tuning coefficient is -10ppm/V/sup 2/. An oscillator interface circuit comprising of a trans-impedance amplifier and an automatic tunable charge pump providing an automatic temperature-compensating bias voltage was also designed and fabricated in a standard 0.5/spl mu/m CMOS process. Preliminary tests show temperature drift reduction of a 4MHz resonator from 2400ppm to 240ppm over a 90/spl deg/C range.

A Low Phase Noise 100MHz Silicon BAW Reference Oscillator

This paper reports on the design and implementation of a process, temperature and supply compensated 7-MHz clock oscillator in a 0.25 /spl mu/m, double poly, 5-metal CMOS process. The clock generator is based on a 3-stage differential ring oscillator. The compensation technique incorporates a unique combination of a process corner sensing scheme and a temperature compensating network to appropriately change the control voltage of the differential ring oscillator. Measurements made across a temperature range of -40/spl deg/C to 125/spl deg/C and 64 samples collected over 3 runs indicate an average variation of /spl plusmn/0.82% (/spl plusmn/46 ppm//spl deg/C) in the clock frequency with temperature, /spl plusmn/2.1% with process across chips at room temperature, and a worst-case combined variation of /spl plusmn/2.6% (with process, temperature and supply). The variation of frequency with power supply was /spl plusmn/0.31% for a supply voltage range of 2.4-2.75 V. The measurement results are in good agreement with the simulation results. The oscillator is intended to serve as a start-up clock for microcontroller applications.

Low-motional-impedance highly-tunable I/sup 2/ resonators for temperature-compensated reference oscillators

The paper describes a 4-MHz temperature compensated reference oscillator based on a capacitive silicon micro-mechanical resonator. The design of the resonator has been optimized to offer large quality factors (22000), while maintaining tunability in excess of 3000 ppm for fine tuning and temperature compensation. Oscillations are sustained with a CMOS amplifier and temperature compensation is performed with a novel resonator bias generator. When interfaced with the bias circuit, the oscillator exhibits a temperature drift of 380 ppm over a 90/spl deg/C range, a 6 times improvement in stability over an uncompensated oscillator. The sustaining amplifier and compensation circuitry were fabricated in a 2P3M 0.5 /spl mu/m CMOS process. The oscillator is designed to prototype highly stable, low phase-noise reference oscillators integrated at the chip or package level.

A 7-MHz process, temperature and supply compensated clock oscillator in 0.25 /spl mu/m CMOS

We developed a 2.5×6.6 mm2 2-D array transducer with integrated transmit/receive application-specific integrated circuit (ASIC) for real-time 3-D intracardiac echocardiography (4-D ICE) applications. The ASIC and transducer design were optimized so that the high-voltage transmit, low-voltage time-gain control and preamp, subaperture beamformer, and digital control circuits for each transducer element all fit within the 0.019-mm2 area of the element. The transducer assembly was deployed in a 10-Fr (3.3-mm diameter) catheter, integrated with a GE Vivid E9 ultrasound imaging system, and evaluated in three preclinical studies. The 2-D image quality and imaging modes were comparable to commercial 2-D ICE catheters. The 4-D field of view was at least 90° × 60° × 8 cm and could be imaged at 30 vol/s, sufficient to visualize cardiac anatomy and other diagnostic and therapy catheters. 4-D ICE should significantly reduce X-ray fluoroscopy use and dose during electrophysiology ablation procedures. 4-D ICE may be able to replace transesophageal echocardiography (TEE), and the associated risks and costs of general anesthesia, for guidance of some structural heart procedures.We developed a 2.5 x 6.6 mm 2D array transducer with integrated transmit/receive ASIC for 4D ICE (real-time 3D IntraCardiac Echocardiography) applications. The ASIC and transducer design were optimized so that the high voltage transmit, low-voltage TGC (time-gain control) and preamp, subaperture beamformer, and digital control circuits for each transducer element all fit within the 0.019 mm2 area of the element. The transducer assembly was deployed in a 10 Fr (3.3 mm diameter) catheter, integrated with a GE Vivid1 E9 ultrasound imaging system, and evaluated in three pre-clinical studies. 2D image quality and imaging modes were comparable to commercial 2D ICE catheters. The 4D field of view was at least 90° x 60° x 8 cm and could be imaged at 30 volumes/sec, sufficient to visualize cardiac anatomy and other diagnostic and therapy catheters. 4D ICE should significantly reduce X-ray fluoroscopy use and dose during electrophysiology (EP) ablation procedures. 4D ICE may be able to replace trans-esophageal echocardiography (TEE), and the associated risks and costs of general anesthesia, for guidance of some structural heart procedures.