Krishnaswamy Ramkumar

A novel low cost 65nm CMOS process architecture with self aligned isolation and W cladded source/drain

A novel CMOS process architecture comprising of 1.5 nm equivalent oxide thickness (EOT) oxide/nitride (O/N) gate dielectric, self aligned shallow trench isolation (SASTI), dual poly/W gate and W cladded source/drain is shown to have low gate dielectric leakage with excellent boron blocking, no dopant cross-diffusion and lower gate and source/drain parasitic resistance.

A scalable, low voltage, low cost SONOS memory technology for embedded NVM applications

A novel low cost, eNVM technology is presented which has the lowest program/erase voltage reported to date. It is based on the integration of a SONOS based NVM module into a foundry CMOS process with only 3 additional masks and no additional HV oxide. An optimized integration scheme ensures that the CMOS device parameters of the eNVM process are closely matched to baseline process. Even with the low 7.5V program/erase voltage, excellent reliability has been demonstrated meeting automotive data retention requirements and 100k cycle endurance on a 4.5Mbit flash memory macro.

High frequency 700V PowerBrane LIGBTs in 0.35µm bulk CMOS technology

A self-isolating, lateral IGBT device with high voltage blocking capability (≫700V), high on-state current density (150A/cm2 at Vds=4V) and very fast turn-off (≪50ns), realized in membrane on bulk Si technology is reported here. The device has been manufactured using a standard 5V, 0.35µm bulk CMOS process on 8″ wafers with the addition of two masks: i) n-drift for the HV blocking region and ii) back-side Deep RIE (DRIE) for membrane formation. In comparison to PowerBrane on SOI, earlier reported by us [1,2], PowerBrane on bulk Si LIGBTs offer higher maximum power density due to better thermal dissipation and more robust operation including unclamped inductive switching and short circuit capability. Reliability of bulk-Si PowerBrane chips in plastic packages has been evaluated through HTRB tests and no failures have been observed after more than 1000 hours of stress. The DRIE step used for selective removal of portions of the silicon substrate, the key feature of PowerBrane technology, offers an effective solution for isolation of the high-voltage power LIGBT(s) from the control circuitry in monolithically integrated Power ICs. In addition, use of bulk Si wafers instead of more expensive SOI substrates reduces the manufacturing costs of PowerBrane-based Power ICs without compromising performance.

Monitoring Nitrogen Profiles in Ultrathin Gate Dielectrics

This paper proposes an inexpensive, manufacturing friendly method of determining the nitrogen profile in ultrathin gate dielectrics to understand its dependence on process parameters. The method uses a variable etch across the wafer with a very dilute HF dip followed by rapid thermal oxidation, and utilizes the oxidation retarding capability of the incorporated nitrogen to draw important conclusions on the nitrogen profile across the thickness of the dielectric. This test can be used in statistical process control for monitoring the nitrogen profile in the dielectric.

Materials and Device Reliability in SONOS Memories

Silicon Nitride based charge trap devices have been studied for more than four decades for applications in non-volatile memories. SONOS memories are a widely used class of non-volatile memories today. Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) stack as the non-volatile memory gate stack has been the focus since the 1990s. Several enhancements in SONOS layer materials have been invented to reduce the programming voltage and improve the reliability of the SONOS memory. This chapter will review the early years of SONOS and then highlight the various innovations that have enhanced SONOS memory performance, reliability and low cost of manufacture. Topics that will be covered include various improvements in the ONO stack such as Band gap engineering, High K-Metal Gate for SONOS, SONOS FinFETs and embedded SONOS.

A Low-Cost Strained Silicon SRAM Technology with Reduced Contact Resistance

This paper presents a simple and cost-effective method to enhance 65nm SRAM technology performance using a single stress liner, resulting in 25% increase in cell read current. A novel slot contact process allows significant improvement of NMOS drive current without PMOS degradation, by relaxing the undesirable strain in the PMOS. This new slot process also results in significant reduction of the S/D contact resistance.