Krzysztof Gucwa

Test-per-Clock Detection, Localization and Identification of Interconnect Faults

The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction. The above-mentioned operations are made at-speed. The testing process has been split into two steps. The first one is the detection step using a short test sequence of little diagnostic resolution. The second step is the localization step by means of a long, full diagnostic resolution sequence and it is made only in the case of the detection of faults in the first step. The final fault identification phase exploits information stored in the signatures. Because the signature is chosen to be 32 bit long aliasing is negligible. The proposed hardware concept is independent of the type of both the detection test sequence and the localization test sequence. The theory given in the paper is illustrated by the simulation results. Moreover the paper proposes to test testing hardware itself what makes the results reliable

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor

We present a test-per-clock BIST scheme using memory for storing test patterns that reduces the number of clock cycle necessary for testing. Thus, the test application time is shorter and energy consumption is lower than those in other solutions. The test hardware consists of a space compactor and a MISR, which provides zero error aliasing for modeled faults. The test pattern generator (TPG) scheme is based on a T-type flip-flop feedback shift register. The generator can be seeded similarly to a D-type flip-flop shift register. It generates test patterns in a test-per-clock mode. The TPG pattern sequence is modified at regular intervals by adding a modulo-2 bit from a modification sequence, which is stored in a memory. The memory can be either a ROM on the chip or a memory in the tester. The test patterns have both random and deterministic properties, which are advantageous for the final quality of the resulting test sequence. The number of bits stored in the memory, number of clock cycles, hardware overhead and the parameters of the resulting zero aliasing space compactor and MISR are given for the ISCAS benchmark circuits. The experiments demonstrate that the BIST scheme provides shorter test sequences than other methods while the hardware overhead and memory requirements are kept low.

Interconnect Faults Identification and Localization Using Modified Ring LFSRs

In the paper a method of the fault detection, identification and localization by means of a ring LFSR (linear feedback shift register) is presented. The properties of a ring LFSR and the method to design a ring LFSR BIST is also given. Practical examinations of a ring LFSR application for localization faults in 8,16,24 and 32-bit buses are presented. Some important observations regarding the types of characteristic polynomials used in ring LFSRs are also included. Finally, the obtained results are summarised.

Effective BIST for crosstalk faults in interconnects

The paper is devoted to a test-per-clock method of an length.

Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor

The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction using a MISR. The above-mentioned operations are made at-speed. The localization is done by means of three long, full diagnostic resolution sequences: Walking 1 (W1), Walking 0 (W0) and a part of Johnson sequence (J). The final fault identification phase exploits information stored in two or three signatures

Crosstalk-Insensitive Method for Testing of Delay Faults in Interconnects Between Cores in SoCs

A method for reliable measurement of interconnect delays is presented in the paper. The mode of test vectors generation never induces crosstalks. That is why the delay measurement is reliable. Also, minimization of ground bounce noises and reduction of power consumption during the test is an additional advantage. The presented method allows also localizing and identifying static faults of both stuck-at (SaX) and short types. The paper deals with the hardware that is necessary for implementing the method. The techniques for test data compression, that allow substantial reduction of data volume transferred between SoC and ATE, are also proposed.

Multi-signature Analysis For Interconnect Test

The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction using a MISR. The above-mentioned operations are made at-speed. The testing process has been split into two steps. The first one is the detection step using a short test sequence of a little diagnostic resolution. The second step (which is made only in the case of the detection of faults in the first step) is the localization step by means of three long, full diagnostic resolution sequences: Walking 1 (W1), Walking 0 (W0) and a part of Johnson sequence (J). The final fault identification phase exploits information stored in two or three signatures. The use of two signatures eliminates aliasing of static faults while adding the third signature enables dependable identification of such faults. The theory given in the paper is partially illustrated by the simulation results. Moreover the paper proposes to test testing hardware itself what makes the results reliable

On simulation of multiplexed architecture for fault-tolerant nanoelectronic systems

The multiplexed architecture is one of well-known approaches to build a reliable system using nanoelectronic devices, where majority organs (MAJ) or NAND gates can be used as restoring elements. That architecture is usually analyzed by means of different probabilistic approaches. In the reported studies the Monte Carlo simulation was applied to analyze the influence of fault probability demonstrated by executing and restoring elements. The multiplexed scheme was investigated respectively for the MAJ and MUX restoration stages but various logic components were applied as executive blocks. The experimental results demonstrated that the behavior of a real circuit can be different from what can be expected based only on the black box approach. It was also revealed that in case of such a structure it is better to use a NAND-based restoration stage as it may provide slightly better results than the MAJ restoration stage.

Reduced-size Signature-based Diagnostic Dictionary for Interconnection Testing

Abstract The paper deals with a new and advanced method intended to reduce size of a diagnostic dictionary that is used for detection, localization and identification of static and delay faults in interconnections that are tested with use of ring linear feedback shift registers (R-LFSR). The proposed method assumes that the bus under test comprises n lines and is structured into b fragments with the size of k lines per each fragment. The method also assumes that each of the aforementioned fragments is tested by means of a separate R-LFSR with its length of 2k bits. In addition, the paper proposes to subdivide the test procedure into four phases whereas odd and even R-LFSRs are activated alternately. It is the way of subdivision that makes it possible to get rid of the mutual interference between two adjacent R-LFSRs when a short between feedback lines of these neighbouring registers takes place. Likelihood of such interactions was the drawback of previous methods and presented the impediment that prevented the fault dictionary from having its size reduced. The innovative solution that is suggested in this study enables to substantially diminish the dictionary, where its actual size is determined by the multiplicity of r defects within each k -bit part of the connecting bus, even when the bus width n >> k .

Avoiding Crosstalk Influence on Interconnect Delay Fault Testing

A method for reliable measurement of interconnect delays is presented in the paper. The mode of test vectors generation never induces crosstalks. That is why the delay measurement is reliable. Also, minimization of ground bounce noises and reduction of power consumption during the test is an additional advantage. The presented method allows also localizing and identifying static faults of both stuck-at (SaX) and short types. The paper deals with the hardware that is necessary for implementing the method.