Kuan-Hung Chen

A Low-Power Digit-Based Reconfigurable FIR Filter

In this brief, we present a digit-reconfigurable finite-impulse response (FIR) filter architecture with a very fine granularity. It provides a flexible yet compact and low-power solution to FIR filters with a wide range of precision and tap length. Based on the proposed architecture, an 8-digit reconfigurable FIR filter chip is implemented in a single-poly quadruple-metal 0.35-mum CMOS technology. Measurement results show that the fabricated chip operates up to 86 MHz when the filter draws 16.5 mW of power from a 2.5-V power supply

A Cognitive Radio System Using Discrete Wavelet Multitone Modulation

A cognitive radio (CR) system is proposed to operate in the GSM band and the discrete wavelet multitone is adopted as the modulation scheme. This modulation has stronger side-lobe attenuation than the popular OFDM modulation and thus generates much lower adjacent channel leakage, making it suitable for applications with dynamically allocated spectrum. Signal and interference analysis of the adopted DWMT modulation is presented and signal processing techniques that tackle synchronization, equalization, and detection are developed. A DWMT baseband receiver is designed and verified by functional simulation. A digital baseband receiver IC is implemented for the proposed DWMT-based CR system. When the whole GSM band is available, the receiver IC can provide up to 153.6 Mbps of data transmission.

A 1.2V 6.7mW impulse-radio UWB baseband transceiver

A 2.7mm/sup 2/ CMOS baseband transceiver IC for impulse-radio UWB communication systems is implemented in a 0.18 /spl mu/m CMOS process. This chip provides up to 62.5Mbit/s data transmission for short-range wireless communications while drawing 6.7mW from a 1.2V power supply.

Algorithm and architecture design for a low-complexity adaptive equalizer

As the need for multimedia communication continues to surge, consumers demand higher and higher transmission data rate. To circumvent the channel impairment caused by multipath fading, more and more receivers resort to adaptive equalizers. However, the complexity of time-domain adaptive equalizers can be too high for some specific applications. In this paper, a novel adaptive algorithm and its low-complexity architecture are proposed. This algorithm, called GSPT LMS algorithm, employs a new Grouped Signed Power-of-Two (GSPT) number representation. An adaptive equalizer using the proposed algorithm has been simulated and shown to be capable of equalization of 8PSK signals in several practical channels. Finally, the proposed adaptive equalizer and two other adaptive equalizers are implemented on a FPGA. Simulation results show that the proposed architecture has the lowest complexity and saves about 50% to 70% of hardware.

Design and implementation of a reconfigurable FIR filter

Finite impulse response (FIR) filters are very important blocks in digital communication systems. Many efforts have been made to improve the filter performance, e.g., less hardware and higher speed. In addition, software radio has recently gained much attention due to the need for integrated and reconfigurable communication systems. To this end, reconfigurability has become an important issue for the future filter design. In this paper, we present a digit-reconfigurable FIR filter architecture with the finest granularity. The proposed architecture is implemented in a single-poly quadruple-metal 0.35-/spl mu/m CMOS technology. Measurement results show that the fabricated chip consumes 16.5 mW of power when operating at 86 MHz under 2.5 V.

Architectural Design of Neural Network Hardware for Job Shop Scheduling

Abstract By combining neural network optimization ideas with “Lagrangian relaxation” for constraint handling, a novel Lagrangian relaxation neural network (LRNN) has recently been developed for job shop scheduling. This paper is to explore architectural design issues for the hardware implementation of such neural networks. A digital circuitry with a micro-controller and an optimization chip is designed, where a parallel architecture and a pipeline architecture are explored for the optimization chip. Simulation results show that the LRNN hardware will provide near-optimal solutions for practical job shop scheduling problems. It is estimated that the parallel architecture will obtain one order of magnitude speed gain, and the pipeline architecture will obtain two orders speed gain as compared with the currently used method.

Grouped signed power-of-two algorithms for low-complexity adaptive equalization

With increasing demand for higher data rate, modern communication systems have grown more complex. Equalization has become more and more important as it is effective in mitigating the multipath fading often occurred in high-data-rate communication systems. However, the implementation complexity of adaptive equalizers is usually too high for mobile communication applications. In this paper, a novel adaptive equalization algorithm and its low-complexity architecture are proposed. This algorithm employs a new grouped signed power-of-two (GSPT) number representation. The GSPT algorithm and several enhanced versions are simulated as adaptive equalizers in a phase-shift keying communication receiver for several practical channels and the GSPT-based equalizers perform as well as the least mean square (LMS) equalizer. Moreover, for comparison, two GSPT-based equalizers and two other equalizers are implemented in field-programmable gate arrays. The GSPT-based equalizers require only about 25%-30% of the hardware resources needed in the LMS equalizer. Also the GSPT-based equalizers are more than twice as fast as the LMS equalizer.

A 1600-MIPS parallel processor IC for job-shop scheduling

A job shop is a typical environment for manufacturing low-volume and high-variety discrete parts, where parts are of various due dates, priorities, and sequences of production operations. Good scheduling of when to do what using which resource is critical and challenging for the competitiveness of job shops. The Lagrangian relaxation neural network (LRNN) presented by Luh et al. provides an effective solution to this problem. To further speed up the scheduling of large problems, the parallelism of the LRNN approach is exploited in this paper for hardware implementation. A parallel processor based on the single-instruction multiple-data-stream architecture and its associated instruction set are designed. The architecture is implemented in a single-poly quadruple-metal 0.35-/spl mu/m CMOS technology. Test results shows that the fabricated chip achieves 10 and 30 times speed-up when compared with several commercial digital signal processor chips and a 600-MHz PC, respectively.

SIMD architecture for job shop scheduling problem solving

Job shop is a typical environment for manufacturing high-variety and low-volume discrete parts. Good scheduling is critical and challenging to the competitiveness of job shops. The Lagrangian relaxation neural network (LRNN) provides an approach of quantifiable quality and successful industrial applications. To further speed up scheduling for large-scale problems, in this paper, the parallelism of the LRNN approach is exploited for hardware implementation. New designs include a SIMD architecture, its associated instruction set and detailed circuits. Logic level simulation of the circuit design shows consistent schedules with those obtained by a software implementation. The hardware implementation is expected to have a one to two orders speed-up over the software one.

A 1.8V 165mW Discrete Wavelet Multi-Tone Baseband Receiver for Cognitive Radio Applications

A 11.7mm2 baseband receiver IC for a cognitive radio system, operating in the GSM band and using discrete wavelet multi-tone modulation is implemented in 0.18mum 1P6M CMOS technology. This chip provides up to 153.6Mb/s uncoded bit rate while consuming 165mW from a 1.8V supply.