Kuang Wei Cheng

High-Efficiency Wireless Power Transfer for Biomedical Implants by Optimal Resonant Load Transformation

Wireless power transfer provides a safe and robust way for powering biomedical implants, where high efficiency is of great importance. A new wireless power transfer technique using optimal resonant load transformation is presented with significantly improved efficiency at the cost of only one additional chip inductor component. The optimal resonant load condition for the maximized power transfer efficiency is explained. The proposed technique is implemented using printed spiral coils with discrete surface mount components at 13.56 MHz power carrier frequency. With an implantable coil having an area of 25 mm × 10 mm and a thickness of 0.5 mm, the power transfer efficiency of 58% is achieved in the tissue environment at 10-mm distance from the external coil. Compared to previous works, the power efficiency is much higher and the structure is compact with planar integration, easy to tune, and suitable for batch production, as well as biocompatible owing to no incorporation of ferromagnetic core.

A 100-Channel 1-mW Implantable Neural Recording IC

This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems.

A Current Reuse Quadrature GPS Receiver in 0.13

A fully-integrated quadrature low-IF L1-band GPS receiver consumes only 6.4 mW in 0.13 μm CMOS. The RF front-end features a gate-modulated quadrature VCO for low phase noise and accurate quadrature phase signal generation. It merges the LNA, quadrature mixer, and quadrature VCO in a single current-reuse stacked topology that provides a conversion gain 42.5 dB with a power consumption of 1 mW. A continuous-time (CT) quadrature bandpass sigma-delta analog-to-digital converter (ADC) provides inherent anti-alias filtering, which simplifies the overall system. The second-order CT ΣΔ ADC achieves 65 dB dynamic range and dissipates only 4.2 mW using resistor DAC feedback. The receiver exhibits an NF of 6.5 dB and an IIP3 of - 30 dBm; the PLL phase noise is -110 dBc/Hz @ 1 MHz frequency offset with quadrature error less than 1°.

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A quadrature voltage-controlled oscillator (QVCO) based on the time-varying gate-modulated coupling of two LC tank VCOs is introduced. Using a standard 0.18μm CMOS process, the new topology is compared to the conventional series QVCO in terms of start-up loop gain, quadrature phase accuracy, phase noise, tuning range, and voltage headroom characteristics. In addition to comparable phase noise performance, the gate-modulated QVCO (GM-QVCO) also exhibits superior quadrature phase accuracy, and suitability for low power supply voltage designs that use cascode current sources and active loads. It draws 2.4 mA from a 1.8 V power supply, displays a phase noise of −122 dBc/Hz @ 1MHz offset, and has a quadrature phase error of 0.4°.

m CMOS

New design techniques are needed for ultra-low-power battery-operated CMOS transceivers with ever-shrinking minimum feature sizes and power supply voltages. A fully-integrated low-IF receiver front-end for GPS applications (Fig. 24.8.1) is presented that addresses this challenge. Integrated in 0.13µm CMOS, its key attribute is µ3X lower power than any previous design: The RF front-end, PLL, IF amplifiers and continuous-time (CT) quadrature ΔΣ ADC consume 1mW, 0.2mW, 1mW, and 5mW, respectively. The RF front-end exploits current reuse in a stacked quadrature LNA-mixer-VCO (QLMV) cell [1]. In addition, it employs double-balanced mixers and features a novel gate-modulated VCO topology for quadrature signal generation that provides low phase noise, high quadrature accuracy and low power. A second-order bandpass CT ADC achieves low power using a quadrature feedback architecture with polyphase filters, resistor DACs and continuous-time comparators.

A gate-modulated CMOS LC quadrature VCO

This paper presents a fully integrated wake-up receiver (WuRx) with direct active RF detection. The RF front-end features a high-sensitivity RF detector embedded with input matching network, obviating the need of RF amplification and LO generation for frequency downconversion. This complete receiver contains an RF detector, IF amplifiers, and a continuous-time ΣΔ ADC to provide inherent anti-alias filtering, which simplifies the overall design in 0.18-μm CMOS process. It achieves a sensitivity of -65 dBm for data rate of 100 kbps, operating in 2.4 GHz ISM band with only 10 μW. By adjusting the input matching, it can also operate for 5.8 GHz band, providing -50 dBm sensitivity without additional power consumption.

A 7.2mW quadrature GPS receiver in 0.13µm CMOS

For real-time monitoring of brain activities, a highdata-rate, low-power, and highly mobile neural recording system is desirable. This paper presents a complete chipset for a 100-channel wireless neural recording system, which consists of 3 ICs - a neural interface (NI) IC and a wireless power RX and data TX IC for an implant unit (IU), and a wireless data RX IC for an external head unit (EHU). With a dual S/H NI architecture and a burst-mode (BM) wideband (WB) FSK TX, the IU achieves a 100-channel recording and wireless transmission at 54.24Mb/s while consuming only 6.6mW. Using power coupling with optimal resonant load transformation and high-efficiency rectifier and LDO circuits, the whole wireless power link achieves 40% efficiency over 1cm distance with 0.5cm tissue in between. The EHU needs to transmit the RF power lower than 30mW to operate the IU. The EHU is implemented using a crystal-less BM WB FSK RX consuming only 14.4mW at 27.12Mb/s.

A 2.4/5.8 GHz 10 μW wake-up receiver with −65/−50 dBm sensitivity using direct active rf detection

Wearable technology is opening the door to future wellness and mobile experience. Following the first generation wearable devices in the form of headsets, shoes and fitness monitors, second generation devices such as smart glasses and watches are making an entrance to the market with a great potential to eventually replace the current mobile device platform eventually (Fig. 30.7.1). Wearable devices can be carried by users in a most natural way and provide all-round connectivity 24-7 without the hassle of stopping all other activities, which enables a totally different mobile experience. For wearable devices, body channel communication (BCC) is an excellent alternative of conventional wireless communication through the air, to obviate the need of high-power transceivers and bulky antennas. However, present BCC transceivers [1]-[5] that mainly target biomedical and sensing applications offer rather limited data rates up to 10Mb/s, which is insufficient in transferring multimedia data for emerging wearable smart devices and content-rich information for high-end medical devices (e.g. multi-channel neural recording microsystems). In this paper, a highly energy-efficient and robust wideband BCC transceiver is presented, which achieves a maximum data rate of 60Mb/s by employing 1) a high input impedance and an equalizer at the RX front-end, 2) transient-detection RX architecture using differentiator-integrator combination coupled with injection-locking-based clock recovery, and 3) 3-level direct digital Walsh-coded signaling at the TX.

100-Channel wireless neural recording system with 54-Mb/s data link and 40%-efficiency power link

This letter presents the design and analysis for a low-phase-noise and low-power Colpitts quadrature voltage-controlled oscillator (QVCO). The Colpitts QVCO employs current switching to lower the phase noise, gm enhancement to improve the startup condition in the oscillator core, and device reuse to realize anti-phase injection locking for QVCO operation. The proposed Colpitts QVCO has superior phase noise than cross-coupled LC tank VCO and outperforms conventional QVCO in phase noise, quadrature phase accuracy, and tuning range. The fabricated 0.18 μm CMOS Colpitts QVCO draws 500 μA from a 1.5 V power supply and exhibits a phase noise of -118 dBc/Hz at 1 MHz offset and a quadrature phase error of 0.3° at the center frequency of 488 MHz.

30.7 A 60Mb/s wideband BCC transceiver with 150pJ/b RX and 31pJ/b TX for emerging wearable applications

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.