Xiaodan Zou

A 100-Channel 1-mW Implantable Neural Recording IC

This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems.

A 1-V 60-µW 16-channel interface chip for implantable neural recording

This paper presents a low-voltage low-power 16-channel interface chip dedicated for implantable neural signal recording. It consists of 16 front-end channels with tunable band-pass filtering and gain settings, multiplexed to a 10-bit SAR ADC for simultaneous recording. To comply with the implantation safety issue while maintaining comparable performance, the overall system is optimized to achieve low power dissipation and efficient power distribution among each individual blocks. A power efficient OTA topology is adopted in the front-end amplifier and a novel dual-capacitive-array SAR ADC is chosen to achieve better power efficiency. A prototype fabricated in a 0.35-µm CMOS technology achieves a NEF of 2.16 and THD of 0.53% at full output swing while providing output data rate of 16 kS/s per channel. The interface consumes 60.3-µW total power from a 1-V supply.

A 1-V 450-nW fully integrated biomedical sensor interface system

This paper presents a 1 V 450 nW fully integrated bio-signal acquisition IC in 0.35 mum CMOS technology which includes a tunable band-pass filter, a variable gain amplifier, and a 12-bit ADC. The ultra-low power is achieved by using an energy-efficient system architecture and a novel tunable band-pass filter. The measurement shows that the overall system draws only 445 nA current from a 1 V supply in the detection mode and 895 nA in the diagnosis mode for electrocardiogram (ECG) applications.

Wireless ECG plaster for body sensor network

Miniaturization of electrocardiograph (ECG) monitoring devices has received much attention due to the growing emphasis on healthcare. In this paper, we present a wearable wireless ECG monitoring device, ECG Plaster. A description of design considerations with regards to the constituents of the device is provided, together with its implementation on a small size board measuring 55 by 23 mm, to ensure wearability.

A 0.5-V 1.13-μW/channel neural recording interface with digital multiplexing scheme

This paper presents a power-efficient system architecture for the design of multiple-channel neural recording interface. A new multiple-channel SAR ADC is proposed to facilitate multiplexing among channels, thus eliminates the need for analog multiplexer and associated buffers. The proposed ADC is verified through a 16-channel recording chip fabricated in a standard 0.13-μm CMOS technology with an active area of 1.17 mm2. The chip consumes 18 μW from a 0.5-V supply and attains a noise efficiency factor of 3.09. The average per channel power and area are 1.13 μW and 0.073 mm2, respectively, which are the lowest among existing multiple-channel designs.

A 1-V 1.1-μW sensor interface IC for wearable biomedical devices

An ultra-low-power, low-noise sensor interface IC dedicated for bio-signal acquisition is presented in this paper. The proposed system architecture is optimized to achieve a better trade-off between power consumption and noise figure. A 0.05 ~ 200 Hz bandpass function is embedded within the front-end amplifier, and a wide bandwidth buffer is inserted between the front-end amplifier and ADC to facilitate a power-efficient interface. The system also includes an 11-bit SAR ADC with nonlinearity of less than plusmn0.7 LSB. The measured input-referred noise is 2.1 muV integrated across the pass-band, achieving noise efficiency factor of 2.9, and the power consumption for the overall system is 1.1 muW under 1 V supply.

100-Channel wireless neural recording system with 54-Mb/s data link and 40%-efficiency power link

For real-time monitoring of brain activities, a highdata-rate, low-power, and highly mobile neural recording system is desirable. This paper presents a complete chipset for a 100-channel wireless neural recording system, which consists of 3 ICs - a neural interface (NI) IC and a wireless power RX and data TX IC for an implant unit (IU), and a wireless data RX IC for an external head unit (EHU). With a dual S/H NI architecture and a burst-mode (BM) wideband (WB) FSK TX, the IU achieves a 100-channel recording and wireless transmission at 54.24Mb/s while consuming only 6.6mW. Using power coupling with optimal resonant load transformation and high-efficiency rectifier and LDO circuits, the whole wireless power link achieves 40% efficiency over 1cm distance with 0.5cm tissue in between. The EHU needs to transmit the RF power lower than 30mW to operate the IU. The EHU is implemented using a crystal-less BM WB FSK RX consuming only 14.4mW at 27.12Mb/s.

A 1V 22µW 32-channel implantable EEG recording IC

Epilepsy is one of the most common neurological disorders and affects more than 50 million individuals worldwide. Neurosurgery is an option for patients and intracranial EEG monitoring needs to be performed before surgery, which requires a multi-channel implantable EEG device. This paper presents a 1V 32-channel reconfigurable sensor interface IC for intracranial EEG recording. The power consumption of the overall system including amplification, filtering, and 10b ADC is 22µW, which makes it suitable for other implantable applications such as deep-brain stimulation.

Neural recording front-end IC using action potential detection and analog buffer with digital delay for data compression

This paper presents a neural recording analog front-end IC intended for simultaneous neural recording with action potential (AP) detection for data compression in wireless multichannel neural implants. The proposed neural recording front-end IC detects the neural spikes and sends only the preserved AP information for wireless transmission in order to reduce the overall power consumption of the neural implant. The IC consists of a low-noise neural amplifier, an AP detection circuit and an analog buffer with digital delay. The neural amplifier makes use of a current-reuse technique to maximize the transconductance efficiency for attaining a good noise efficiency factor. The AP detection circuit uses an adaptive threshold voltage to generate an enable signal for the subsequent functional blocks. The analog buffer with digital delay is employed using a finite impulse response (FIR) filter which preserves the AP waveform before the enable signal as well as provides low-pass filtering. The neural recording front-end IC has been designed using standard CMOS 0.18-μm technology occupying a core area of 220 μm by 820 μm.

Independent Mobility Achieved through a Wireless Brain-Machine Interface

Individuals with tetraplegia lack independent mobility, making them highly dependent on others to move from one place to another. Here, we describe how two macaques were able to use a wireless integrated system to control a robotic platform, over which they were sitting, to achieve independent mobility using the neuronal activity in their motor cortices. The activity of populations of single neurons was recorded using multiple electrode arrays implanted in the arm region of primary motor cortex, and decoded to achieve brain control of the platform. We found that free-running brain control of the platform (which was not equipped with any machine intelligence) was fast and accurate, resembling the performance achieved using joystick control. The decoding algorithms can be trained in the absence of joystick movements, as would be required for use by tetraplegic individuals, demonstrating that the non-human primate model is a good pre-clinical model for developing such a cortically-controlled movement prosthetic. Interestingly, we found that the response properties of some neurons differed greatly depending on the mode of control (joystick or brain control), suggesting different roles for these neurons in encoding movement intention and movement execution. These results demonstrate that independent mobility can be achieved without first training on prescribed motor movements, opening the door for the implementation of this technology in persons with tetraplegia.