Jia Hao Cheong

A 100-Channel 1-mW Implantable Neural Recording IC

This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 μVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-μm standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems.

A 400-nW 19.5-fJ/Conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18-

As the low-power-consumption requirement of integrated circuits for biomedical applications (e.g., wearable sensor nodes operating with and without batteries, and implantable medical devices powered by batteries and wireless charging) becomes more stringent, the data converter design evolves toward mircrowatt and submircrowatt power consumption. In this brief, a 400-nW successive approximation analog-to-digital converter (SAR ADC) is presented. A trilevel switching scheme with common-mode reset, redundant algorithm, and a time-domain comparator is proposed and implemented to achieve ultralow power consumption. The redundant algorithm mitigates the offset error caused by the level mismatch of the trilevel switching scheme, whereas the trilevel switching scheme simplifies the switching logic of the redundant algorithm. Fabricated in a 0.18-μm CMOS process, the proposed SAR ADC achieves a signal-to-noise-and-distortion ratio of 50 dB, which is equivalent to an 8-bit effective number of bits, at an 80-kS/s conversion rate. The figure of merit is 19.5 fJ/conversion step.

\mu\hbox{m}

A high-voltage (HV) transmitter integrated circuit for ultrasound medical imaging applications is implemented using 0.18-μm bipolar/CMOS/DMOS technology. The proposed HV transmitter achieves high integration by only employing standard CMOS transistors in a stacked configuration with dynamic gate biasing circuit while successfully driving the capacitive micromachined ultrasound transducer device immersed in an oil environment without breakdown reliability issues. The HV transmitter including the output driver and the voltage level shifters generates over 10-Vp-p pulses at 1.25-MHz frequency and occupies only 0.022 mm2 of core die area.

CMOS

A fully integrated SoC for multimodality intracranial neuromonitoring is presented in this paper. Three sensors including a capacitive MEMS pressure sensor, an electrochemical oxygen sensor and a solid-state temperature sensor are integrated together in a single chip with their respective interface circuits. Chopper stabilization and dynamic element matching techniques are applied in sensor interface circuits to reduce circuit noise and offset. On-chip calibration is implemented for each sensor to compensate process variations. Measured sensitivity of the pressure, oxygen, and temperature sensors are 18.6 aF/mmHg, 194 pA/mmHg, and 2 mV/°C, respectively. Implemented in 0.18 m CMOS, the SoC occupies an area of 1.4 mm × 4 mm and consumes 166 μW DC power. A prototype catheter for intracranial pressure (ICP) monitoring has been implemented and the performance has been verified with ex vivo experiment.

A CMOS High-Voltage Transmitter IC for Ultrasound Medical Imaging Applications

With the growing number of wearable devices and applications, there is an increasing need for a flexible body channel communication (BCC) system that supports both scalable data rate and low power operation. In this paper, a highly flexible frequency-selective digital transmission (FSDT) transmitter that supports both data scalability and low power operation with the aid of two novel implementation methods is presented. In an FSDT system, data rate is limited by the number of Walsh spreading codes available for use in the optimal body channel band of 40-80 MHz. The first method overcomes this limitation by applying multi-level baseband coding scheme to a carrierless FSDT system to enhance the bandwidth efficiency and to support a data rate of 60 Mb/s within a 40-MHz bandwidth. The proposed multi-level coded FSDT system achieves six times higher data rate as compared to other BCC systems. The second novel implementation method lies in the use of harmonic frequencies of a Walsh encoded FSDT system that allows the BCC system to operate in the optimal channel bandwidth between 40-80 MHz with half the clock frequency. Halving the clock frequency results in a power consumption reduction of 32%. The transmitter was fabricated in a 65-nm CMOS process. It occupies a core area of 0.24 × 0.3 mm 2. When operating under a 60-Mb/s data-rate mode, the transmitter consumes 1.85 mW and it consumes only 1.26 mW when operating under a 5-Mb/s data-rate mode.

A Monolithically Integrated Pressure/Oxygen/Temperature Sensing SoC for Multimodality Intracranial Neuromonitoring

For real-time monitoring of brain activities, a highdata-rate, low-power, and highly mobile neural recording system is desirable. This paper presents a complete chipset for a 100-channel wireless neural recording system, which consists of 3 ICs - a neural interface (NI) IC and a wireless power RX and data TX IC for an implant unit (IU), and a wireless data RX IC for an external head unit (EHU). With a dual S/H NI architecture and a burst-mode (BM) wideband (WB) FSK TX, the IU achieves a 100-channel recording and wireless transmission at 54.24Mb/s while consuming only 6.6mW. Using power coupling with optimal resonant load transformation and high-efficiency rectifier and LDO circuits, the whole wireless power link achieves 40% efficiency over 1cm distance with 0.5cm tissue in between. The EHU needs to transmit the RF power lower than 30mW to operate the IU. The EHU is implemented using a crystal-less BM WB FSK RX consuming only 14.4mW at 27.12Mb/s.

High Bandwidth Efficiency and Low Power Consumption Walsh Code Implementation Methods for Body Channel Communication

Wearable technology is opening the door to future wellness and mobile experience. Following the first generation wearable devices in the form of headsets, shoes and fitness monitors, second generation devices such as smart glasses and watches are making an entrance to the market with a great potential to eventually replace the current mobile device platform eventually (Fig. 30.7.1). Wearable devices can be carried by users in a most natural way and provide all-round connectivity 24-7 without the hassle of stopping all other activities, which enables a totally different mobile experience. For wearable devices, body channel communication (BCC) is an excellent alternative of conventional wireless communication through the air, to obviate the need of high-power transceivers and bulky antennas. However, present BCC transceivers [1]-[5] that mainly target biomedical and sensing applications offer rather limited data rates up to 10Mb/s, which is insufficient in transferring multimedia data for emerging wearable smart devices and content-rich information for high-end medical devices (e.g. multi-channel neural recording microsystems). In this paper, a highly energy-efficient and robust wideband BCC transceiver is presented, which achieves a maximum data rate of 60Mb/s by employing 1) a high input impedance and an equalizer at the RX front-end, 2) transient-detection RX architecture using differentiator-integrator combination coupled with injection-locking-based clock recovery, and 3) 3-level direct digital Walsh-coded signaling at the TX.

100-Channel wireless neural recording system with 54-Mb/s data link and 40%-efficiency power link

This paper presents a fully integrated inductively powered implantable circuits for blood flow measurement, which are embedded within vascular prosthetic grafts for early detection of graft degradation or failure. The ASIC interfaces with micro-fabricated pressure sensors and uses a 13.56MHz carrier frequency for power transfer and command/data communication. A backscatter-modulated passive telemetry is used for transmitting sensor readout information to an external monitoring device. The chip has been fabricated in 0.18μm CMOS process, occupies a total active area of 1.5×1.78mm2 and consumes a total power of 21.6μW. The rectifier achieves an efficiency of 66% The sub-μW 10-bit SAR ADC achieves an ENOB of 8.5 bits at 106KS/s conversion rate.

30.7 A 60Mb/s wideband BCC transceiver with 150pJ/b RX and 31pJ/b TX for emerging wearable applications

This paper presents a 2.45-GHz wireless link to power on the miniaturized biomedical devices. In this link, a chip antenna is adopted for RF power transmitting, and a resonant network consisting of a compact inductor and a chip capacitor is employed for energy harvesting. A prototype is fabricated and measured in the time- and frequency-domain. The measured results show that this power transfer link meets the system requirement. In addition, in the case of a capacitor with 20% variation, this link can still achieve the system required efficiency. It therefore eliminates the adaptive matching circuit and simplifies the system design.

A 21.6μW inductively powered implantable IC for blood flow measurement

Individuals with tetraplegia lack independent mobility, making them highly dependent on others to move from one place to another. Here, we describe how two macaques were able to use a wireless integrated system to control a robotic platform, over which they were sitting, to achieve independent mobility using the neuronal activity in their motor cortices. The activity of populations of single neurons was recorded using multiple electrode arrays implanted in the arm region of primary motor cortex, and decoded to achieve brain control of the platform. We found that free-running brain control of the platform (which was not equipped with any machine intelligence) was fast and accurate, resembling the performance achieved using joystick control. The decoding algorithms can be trained in the absence of joystick movements, as would be required for use by tetraplegic individuals, demonstrating that the non-human primate model is a good pre-clinical model for developing such a cortically-controlled movement prosthetic. Interestingly, we found that the response properties of some neurons differed greatly depending on the mode of control (joystick or brain control), suggesting different roles for these neurons in encoding movement intention and movement execution. These results demonstrate that independent mobility can be achieved without first training on prescribed motor movements, opening the door for the implementation of this technology in persons with tetraplegia.