Kumar N. Lalgudi

DelaY: An Efficient Tool for Retiming with Realistic Delay Modeling

The retiming transformation can be used to optimize synchronous circuits for maximum speed of operation by relocating their storage elements. In this paper, we describe DelaY, a tool for retiming edge-triggered circuits under a realistic delay model that handles load-dependent gate delays, variable register setup times, interconnect delays, and clock skew. The operation of DelaY relies on a novel linear programming formulation of the retiming problem in this model. For the special case where clock skew is monotonic and all registers have equal propagation delays, the retiming algorithm in our tool runs in polynomial time and can transform any given edge-triggered circuit to achieve a specifi clock period in O(V/sup 3/F) steps, where V is the number of logic gates in the circuit and F is bounded by the number of registers in the circuit.

Computing strictly-second shortest paths

We investigate the problem of computing the strictly-second shortest path connecting a given pair of vertices in a directed graph. We show that this problem is intractable when the path is restricted to be simple. When cycles are allowed, we give an algorithm that solves it in asymptotically the same number of steps as it takes to compute the shortest path between the given vertex pair.

Optimizing computations for effective block-processing

Block-processing can decrease the time and power required to perform any given computation by simultaneously processing multiple samples of input data. The effectiveness of block-processing can be severely limited, however, if the delays in the dataflow graph of the computation are placed suboptimally. In this paper we investigate the application of retiming for improving the effectiveness of block-processing in computations. In particular, we consider the k-delay problem: Given a computation dataflow graph and a positive integer k, we wish to compute a retimed computation graph in which the original delays have been relocated so that k data samples can be processed simultaneously and fully regularly. We give an exact integer linear programming formulation for the k-delay problem. We also describe an algorithm that solves the k-delay problem fast in practice by relying on a set of necessary conditions to prune the search space. Experimental results with synthetic and random benchmarks demonstrate the performance improvements achievable by block-processing and the efficiency of our algorithm.

Retiming edge-triggered circuits under general delay models

The retiming transformation can be used to optimize synchronous circuits for maximum speed of operation by relocating their storage elements. For relatively simple delay models, an optimal retiming of a given circuit can be computed in polynomial time. Under more comprehensive delay models, however, the retiming problem is solved by resorting to branch-and-bound techniques. In this paper, we investigate retiming under delay models that encompass load-dependent gate delays, register delays, interconnect delays, and clock skew. For the most general of our delay models, we express the retiming problem as a set of integer linear programming (ILP) constraints that can be solved using ILP techniques. For less general delay models, which encompass circuits with monotonic clock skews and load-dependent gate delays, we give an integer monotonic programming formulation for the retiming problem and an asymptotically efficient retiming algorithm. Our algorithm re-times any given edge-triggered circuit to achieve a specified clock period in O(V/sup 3/ F) steps, where V is the number of combinational logic gates in the circuit and F is a constant no greater than the circuits register count. We have implemented our algorithms in DELAY, a software tool for optimizing synchronous circuits, and have evaluated their performance on benchmark circuits.

Efficient retiming under a general delay model

The polynomial-time retiming algorithms that were developed in the eighties assumed simple delay models that neglected several timing issues that arise in logic design. Recent retiming algorithms for more comprehensive delay models rely on non-linear formulations and run in worst-case exponential time using branch-and-bound techniques. In this paper, we investigate the retiming problem for edge-triggered circuits under a general delay model that handles load-dependent gate delays, register delays, interconnect delays, and clock skew. We show that in this model the retiming problem can be expressed as a set of integer linear programming constraints that can be solved using general ILP techniques. For the special case where clock skew is monotonic and all registers have equal propagation delays, we give an integer phonotonic programming formulation of the retiming problem, and we present an efficient algorithm for solving it. Our algorithm retimes any given edge-triggered circuit to achieve a specified clock period in O(V/sup 3/F) steps, where V is the number of logic gales in the circuit and F is bounded by the number of registers in the circuit. A straightforward extension of our algorithm determines a minimum clock period retiming in O(V/sup 3/Flg V) steps.

Architecture of a Min-Max Simulator on MARS

Uniprocessor implementations of logic simulators using the ambiguity (min-mm) delay model are too slow for the design cycle times of present day very large scale inte- grated (VLSI) chips. For this reason, parallelization of logic simulation using this model assumes importance. In this pczper, we present the architecture of a min-max delay simula- tor on the MARS parallel computer. The simulation algorithm, partitioned across processors configured in a pipeline, pro- cseds in two phases. The problems of processing common ambiguity regions and guaranteed separation between events, are taken care of by dedicated processing elements. Synchro- nous sequential elements and memory blocks are functionally modeled. Ajve valued algebra is used for element evaluation. Implementation of this simulator is currently under way.

Optimizing systems for effective block-processing: the k -delay problem

Block-processing is a powerful and popular technique for increasing computation speed by simultaneously processing several samples of data. The effectiveness of block-processing is often reduced, however, due to suboptimal placement of delays in the dataflow graph of a computation. In this paper we investigate an application of the retiming transformation for improving the effectiveness of block-processing in computation structures. Specifically, we consider the k-delay problem in which we wish to retime any given computation so that given an integer k the resulting computation can process k data samples simultaneously in a fully regular manner. Our main contribution is an O(V/sup 3/E+V/sup 4/ log V)-time algorithm for the L-delay problem, where V is the number of computation blocks and E is the number of interconnections in the computation.

Optimizing Systems for Effective Block-Processing: Optimizing Systems for Effective Block-Processing:

|Block-processing is a powerful and popular technique for increasing computation speed by simultaneously processing several samples of data. The effectiveness of block-processing is often reduced, however, due to suboptimal placement of delays in the data flow graph of a computation. In this paper we investigate an application of the retiming transformation for improving the effectiveness of block-processing in computation structures. Specifically, we consider the k-delay problem in which given an integer k the resulting computation can process k data samples simultaneously in a fully regular manner. Our main contribution is an O(V^3 E + V^4 log V)-time algorithm for the k-delay problem, where V is the number of computation blocks and E is the number of interconnections in the computation.