Debashis Bhattacharya

Transistor-level optimization of digital designs with flex cells

The flex-cell approach, either alone or in combination with standard cells, provides an optimally tuned set of building blocks for integrated circuit design when optimality is measured using accepted and quantifiably definable metrics such as clock speed, die size, and power consumption.

TSUNAMI: a path oriented scheme for algebraic test generation

An algorithm is presented for generating tests for single stuck line faults using a combination of algebraic processing and conventional path oriented search. Unlike conventional test generation algorithms, this algorithm uses algebraic methods to determine the complete set of input assignments that will propagate an error signal through a gate in a path to a primary output. The algorithm uses ordered binary decision diagrams (BDDs) for algebraic processing. For a large number of circuits that are amenable to analysis using BDDs, the algorithm is faster than previous algebraic methods. The algorithm has been implemented as the program TSUNAMI. Experimental results demonstrate that for most circuits TSUNAMI can generate test sets for all faults in fairly small amounts of time and is very efficient for hard-to-detect and redundant faults. Moreover, since a large set of tests is generated for each fault, these sets can be compacted to a very high degree. Using benchmark circuits as a reference, TSUNAMI obtains test sets up to 70% smaller than test sets generated by conventional algorithms.<<ETX>>

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.

A three-stage partial scan design method using the sequential circuit flow graph

A new three-stage process for partial scan design is presented. The first two stages focus on cycle-breaking, and on limiting the maximum length of consecutive self-loops, as proposed by previous researchers. For the third stage, combinational blocks and their effects on sequential test generation are evaluated using a graph-theoretic representation designated the circuit flow graph. Costs calculated from the circuit flow graph representation are then used to select additional scan flip-flops. Sequential test generation results show that our selection of scan flip-flops are generally smaller than those reported by earlier researchers, and lead to comparable fault coverage with smaller test generation time.<<ETX>>

Hierarchical Modeling for VLSI Circuit Testing

1 Introduction.- 1.1 Background.- 1.2 Prior Work.- 1.2.1 Test Generation for Combinational Circuits.- 1.2.2 Test Generation for Sequential Circuits.- 1.2.3 High-level Test Generation.- 1.2.4 Fault Simulation.- 1.2.5 Design for Testability.- 1.3 Outline.- 2 Circuit and Fault Modeling.- 2.1 Vector Sequence Notation.- 2.2 Circuit and Fault Models.- 2.2.1 Circuit Model.- 2.2.2 Fault Model.- 2.3 Case Study: k-Regular Circuits.- 3 Hierarchical Test Generation.- 3.1 Vector Cubes.- 3.2 Test Generation.- 3.2.1 Repetitive Circuits.- 3.2.2 Pseudo-Sequential Circuits.- 3.2.3 High-Level Test Generation Algorithm.- 3.3 Implementation and Experimental Results.- 3.3.1 Circuit Description.- 3.3.2 Data Structures.- 3.3.3 Program Structure.- 3.3.4 Experimental Results.- 4 Design for Testability.- 4.1 Ad Hoc Techniques.- 4.1.1 Array-Like Circuits.- 4.1.2 Tree-Like Circuits.- 4.2 Level Separation (LS) Method.- 4.2.1 Functions Realizable by One-Dimensional ILAs.- 4.2.2 Functions Realizable by Two-Dimensional ILAs.- 4.3 Case Study: ALU.- 5 Concluding Remarks.- 5.1 Summary.- 5.2 Future Directions.- Appendix A: Proofs of Theorems.- A.1 Proof of Theorem 3.2.- A.2 Proof of Theorem 3.3.- A.3 Proof of Theorem 4.1.

A three-stage partial scan design method to ease ATPG

A new three-stage process for partial scan design is presented. The first two stages focus on cyclebreaking, and on limiting the maximum length of consecutive self-loops, as proposed by previous researchers. For the third stage, combinational blocks and their effects on sequential test generation are evaluated using a graphtheoretic representation designated the circuit flow graph. Costs calculated from the circuit flow graph representation are then used to select additional scan flip-flops. Sequential test generation results show that our selection of scan flip-flops is generally smaller than that reported by earlier researchers, and leads to a comparable fault coverage and smaller test generation time.

Design Optimization with Automated Flex-Cell Creation

The set of flex-cells, either alone or in combination with standard-cells, provides an optimally tuned set of building blocks for the target IC design, where optimality is measured against accepted and definable (i.e. quantifiable) metrics like clock speed, die size, power consumption, etc.. By allowing the transistor-level structures to be manipulated, flex-cells open up a new dimension in the optimization of automatically created designs. Flex-cells allow both the transistor-level structure and sizing to be manipulated freely. Such flexibility does not come for free, as is to be expected. A host of issues ranging from the “correct” choice of flex-cell mapping (to transistors) technology, to minimizing the number of flex-cells to be used in a design, to efficient characterization of flex-cells, to the interplay between flex-cell based optimization and other important issues like physical design information, need to be addressed. Preliminary results using flex-cell based optimization suggest that when employed properly, this methodology holds promise of significant benefit to the process of optimizing automatically created digital designs.

High-level test generation for VLSI

The authors survey high-level approaches to test generation for VLSI circuits, which can significantly reduce test generation time while still providing good fault coverage. High-level approaches view the circuit with less structural detail, that is, from a more abstract viewpoint and often hierarchically. The authors first review some basic circuit and fault models and the two most widely known test-generation algorithms as a basis for comparison between high-level and low-level techniques. The authors then examine the more important high-level approaches, which fall into two broad classes, namely algorithmic and heuristic.<<ETX>>

Architecture of a Min-Max Simulator on MARS

Uniprocessor implementations of logic simulators using the ambiguity (min-mm) delay model are too slow for the design cycle times of present day very large scale inte- grated (VLSI) chips. For this reason, parallelization of logic simulation using this model assumes importance. In this pczper, we present the architecture of a min-max delay simula- tor on the MARS parallel computer. The simulation algorithm, partitioned across processors configured in a pipeline, pro- cseds in two phases. The problems of processing common ambiguity regions and guaranteed separation between events, are taken care of by dedicated processing elements. Synchro- nous sequential elements and memory blocks are functionally modeled. Ajve valued algebra is used for element evaluation. Implementation of this simulator is currently under way.

Designing for high-level test generation

Recent work has shown that test generation complexity and test set size can be reduced by high-level analysis that exploits the natural design hierarchy found in digital circuits. A design modification approach aimed at facilitating high-level testing by enhancing circuit regularity is proposed. This approach can improve the testability of a broad class of useful array- and tree-like circuits, including counters, decoders, and arithmetic logic units (ALUs). This is demonstrated for the specific case of decoders and decoding trees, where the test set size is reduced from O(2/sup n/) to O(n). A systematic design technique called level separation (LS) is presented for generalized tree circuits, which are useful for fast implementation of arithmetic functions like addition and multiplication. Design for testability (DFT) and hierarchical test generation are shown to reduce the test size from O(n) to O(log/sub 2/ n) for such circuits. A case study of a 16-b four-function ALU is presented to illustrate the utility of the LS method. >