Kun-Ho Kwak

The revolutionary and truly 3-dimensional 25F/sup 2/ SRAM technology with the smallest S/sup 3/ ( stacked single-crystal Si) cell, 0.16um/sup 2/, and SSTFT (atacked single-crystal thin film transistor) for ultra high density SRAM

The smallest 25F/sup 2/ SRAM cell size of 0.16um/sup 2/ is realized by S/sup 3/ cell technology and SSTFT with 193nm ArF lithography process. The stacked single-crystal thin film is developed and used for the first time in the SRAM cell to make the SRAM products comparative to the DRAM products in the density and the cost. The load PMOS and pass NMOS transistors are stacked over the planar pull-down NMOS transistors to drastically reduce the cell size. In this study, the dream of truly 3D memory device is achieved by fabricating 64M bit density SRAM.

Highly area efficient and cost effective double stacked S/sup 3/ (stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM

For the first time, the highest density SRAM, such as 512M bit SRAM, is developed by implementing the smallest 25F/sup 2/S/sup 3/ SRAM cell technology, whose cell size is 0.16/spl mu/m/sup 2/, and area saving peripheral SSTFT (stacked single-crystal thin film transistor) technology. The SSTFT are used as the peripheral CMOS transistors as well as the cell transistors to save area to make the SRAM products comparative to the DRAM cell based products in the density and the cost. In the S/sup 3/ SRAM cell, the load PMOS and pass NMOS transistors are stacked over the planar pull-down NMOS transistors to drastically reduce the cell size. Also, in a periphery, the core logic transistors are stacked on the ILD to save the layout area for maximizing cell efficiency for the products.

High Speed and Highly Cost effective 72M bit density S 3 SRAM Technology with Doubly Stacked Si Layers, Peripheral only CoSix layers and Tungsten Shunt W/L Scheme for Standalone and Embedded Memory

Highly cost effective and high speed 72M bit density S3 SRAM technology was successfully achieved for standalone memory and embedded memory with selective epitaxial growth of Si films, low thermal SSTFT process , periphery only Co salicidation, and W shunt wordline scheme.

Fabrication and characteristics of novel load PMOS SSTFT (Stacked Single-crystal Thin Film Transistor) for 3-Dimensional SRAM memory cell

The PMOS SSTFT (stacked single-crystal thin film transistor) is developed for achieving the smallest SRAM cell size, such as 45F/sup 2/, and low power mobile applications with the single crystallization technology of the Si thin films on the insulators. The electrical properties of the SSTFT load pMOS are comparable to those of bulk Si Tr. or SOI Tr. For example, Ion/Ioff ratio is nearly 10/sup 7/ and sub-threshold swing is 150 mV/dec. The SNM(Static Noise Margin) value is 650 mV at Vdd=2.0 V and the SSTFT load pMOS lifetime under the HElP stress is over 10 years at 3.0 V operation voltage. The novel S/sup 3/ (stacked single-crystal Si) SRAM cell used the SSTFT pMOS as the load pMOS which is successfully fabricated.

Ultra-low power and high speed SRAM for mobile applications using single Poly-Si gate 90 nm CMOS technology

High speed and ultra-low power SRAM using single gate CMOS technology was developed. The drive currents of NMOSFET and PMOSFET were 410 /spl mu/A//spl mu/m and 205 /spl mu/A//spl mu/m, respectively. The random access time of 17 ns at 1.65 V operation voltage was achieved for the first time in low power application by the reduction of loading capacitance. Standby current was less than 15 /spl mu/A/chip. The highly manufacturable compact cell of 0.84 /spl mu/m/sup 2/ area was integrated using PR (photo resist) flow technology and novel contact layout.

Highly manufacturable 32 Mb ULP-SRAM technology by using dual gate process for 1.5 V Vcc operation

For 1.5 V low Vcc operation and high performance, a full-CMOS ultra low power (ULP) SRAM using dual gate and Co salicide technology was developed. We evaluated the new technology including (i) 0.11 /spl mu/m fine patterning implemented by phase shift mask (PSM) and optical proximity correction (OPC), (ii) dual gate CMOS transistors with thin gate oxide, (iii) improvement of the Co salicide process to minimize leakage current, including ultra-shallow junction and rapid thermal annealing (RTA) processing. The results have been achieved on a 32 Mb high density 6 T ULP-SRAM cell.

High Density and Ultra-Low Power Mobile SRAM Using the Novel Double S3 (Stacked Single-crystal Silicon) Technology and KrF lithography

The novel mobile SRAM was developed using the double stack S technology and KrF lithography for high density and low power mobile applications. The load PMOS and pass NMOS transistors of the SRAM cell were stacked on the planar pull-down NMOS transistors in different levels, respectively, and the cell transistors were also connected in a cross-coupled way by a single node contact to reduce the cell size. The highly manufacturable 64M bit Mobile SRAM was fabricated with this technology Introduction There are great demands of high density and low power consumption for mobile applications. In order to meet the demand of higher density, the Pseudo SRAM (PSRAM) based on DRAM (Dynamic Random Access Memory) cell structure has started replacing the conventional 6T full CMOS SRAM as a RAM memory of the handheld mobile phones. Recently, in order to reduce the cell area of 6T full CMOS SRAM from 80~100F cell area to 45 F as shown in Fig.1, the single stack S SRAM cell technology has been invented. Nevertheless, the s ingle stack S SRAM cell is not small enough to compete with the pseudo SRAM in the cost and the density [1]. Therefore, the double stacked S SRAM cell as shown in Fig.2 was needed to be comparable to the chip size and the density of the Pseudo SRAM [2]. Also, 100nm KrF lithographic tools were adopted to minimize the investment and the extendibility of the KrF based patterning technology for the productivity and the cost of the mobile SRAM products. In this study, the highly manufacturable Mobile SRAM, which can be operated even at 1.3V, is fabricated with the 25F smallest SRAM cell, KrF lithography, novel crystallization method and multi layer interconnection technology. Process Technology In the double S SRAM cell of Fig.2, the pass transistor is stacked on the load PMOS transistor already stacked on the bulk pull-down NMOS transistor. The top view SEM image of the active region and the pull down transistor on the first level is shown in Fig. 3(a). The plasma nitrided gate oxide of 3.5nm was grown to reduce the thermal budget to suppress the short channel effect of CMOS transistors. After forming the planar transistor on the bulk, the high-density plasma (HDP) oxide was deposited. After inter gate dielectric (IGD) layers were planarized, the crystallized single crystal silicon thin film layer was formed as a active layer of the load PMOS transistor. Then, the load pMOS SSTFT (Stacked Singlecrystal Thin Film Transistor) was fabricated on the IGD layers, as shown in Fig. 3(b). The pass transistor on third level of the double S cell, is shown in Fig.3(c). The wordline, which is the gates of the pass transistors, is connected throughout the whole row of the cell array. Patterning of the word lines is one of the most difficult part of the S cell integration. In addition to forming the SSTFT, the other key factor in process integration of S cell was to form the node contact holes. In the S SRAM cell, the local interconnection layers for cross coupling of nodes and gates are eliminated because all nodes and gates of the transistors are connected with one contact hole which is aligned vertically through the whole layers from the node of the pass transistor on third level to the node of the pull down transistor on the bulk silicon, as shown in Fig.4. The function of through node contact is very important since only one contact has to connect all of the nodes and the gates placed on the different levels. After the node contacts are filled with W plug. The Wdamascene line for the power lines, such as Vss and Vdd, and Al metal lines as bit-line were formed to complete the memory cell structure. The vertical TEM images of the double S SRAM cell array were presented in Fig.4. Electrical Characteristics The node contact has five different contacting parts which connect between the nodes of the cell. Therefore, it has five values of the resistance. It is important to control all of the contact resistance precisely. They are very sensitive to the process conditions, such as the doping concentrations of the gates and actives and the size of the contacted area. By optimizing the process conditions, good distributions of the resistance of each contact part have been obtained as shown in Fig.6. The drive currents of 15uA/um and 2uA/um for NMOS pass SSTFT and PMOS load SSTFT were achieved with <1pA of off-state transistor leakage current, respectively (Fig.6). The distributions of stand-by current of the 64M bit Mobile SRAM are shown in Fig.7. The SNM (Static Noise Margin) of the cell are measured in Fig.8. The SNM curve shows stable margins at operation voltages. The margin was about 200mV at 1.2V. The random access time (tAA) was less than 35nsec (Fig.9) at 85°C, Vdd = 1.65V. These performance are much better than those of the Pseudo RAM and the conventional 6T full CMOS low power SRAM. Fig.10 shows the photograph of 64M bit Mobile SRAM chip fabricated with this technology. Summary High density and low power Mobile SRAM with the smallest 25F S SRAM cell was successfully fabricated by using double S technology and KrF lithography. The difficulties of the formation of the node contact, which connects various nodes and gates by side wall contacting and shared contacting schemes, was overcome by optimization of doping concentration of S/D and multi contact etching process

Novel 3-dimensional 46F/sup 2/ SRAM technology with 0.294um/sup 2/ S/sup 3/ (stacked single-crystal Si) cell and SSTFT (stacked single-crystal thin film transistor)

We have realized a 46F/sup 2/ SRAM cell size of 0.294 /spl mu/m/sup 2/ with 80 nm technology and single stack S/sup 3/ cell technology. SSTFTs and vertical node contacts are major keys in the S/sup 3/ cell technology. The stacked single crystal silicon thin film is developed for the load pMOS SSTFT of the S/sup 3/ SRAM cell. The load pMOS SSTFT is stacked on ILD to reduce the SRAM cell size. Fully working 64 Mbit SRAM is achieved by this S/sup 3/ cell technology. The basic reliability of SSTFT, with 80 nm length, is also investigated in this study.

Highly manufacturable 100 nm 6T low power SRAM with single poly-Si gate technology

As scaling down the device, it is difficult to control the standby leakage and device performance at the same time. In this work, 6-transistor SRAM cell using buried channel PMOS technology was introduced and the device for low power consumption was analyzed. The major source of leakage current on NMOS and PMOS devices was different pathways, and it was controlled by reduction of gate poly-Si oxidation thickness and the optimization of LDD implantation process. The load PMOS lifetime under the HEIP stress was over 10 years at 3.5V of operation voltage. The SNM margin was obtained in subthreshold operation region by increase the current of load transistor and compensated for the process variation. Finally, SRAM cell of 0.84 /spl mu/m/sup 2/ of size with 0.1 /spl mu/m design rule was successfully fabricated.