Kun-Ok Ahn

Highly reliable M1X MLC NAND flash memory cell with novel active air-gap and p+ poly process integration technologies

Our Middle-1X nm MLC NAND (M1X) flash cell is intensively characterized with respect to reliability and manufacturability. For the first time, the novel active air-gap technology is applied to alleviate the drop of channel boosting potential of program inhibition mode, BL-BL interference is reduced to our 2y nm node level by this novel integration technology. Furthermore, it also relaxes the effect of process variation like EFH (Effective Field oxide Height) on cell Vt distribution. Better endurance and retention characteristics can be obtained by p+ doped poly gate. By optimization of active air-gap profile and poly doping level, M1X nm MLC NAND flash memory has been successfully implemented with superior manufacturability and acceptable reliability.

NAND Flash reliability degradation induced by HCI in boosted channel potential

In this paper, we present the impact of hot carrier injection (HCI) during programming operation in NAND Flash, and describe how HCI degrades reliability characteristics. In order to understand reliability degradation induced by HCI, we evaluated the reliability characteristics under various stress conditions including the number of disturbance pulses, pulse shapes and temperatures. We have concluded that the programming pulse and boosting bias should be carefully optimized to reduce the impact of HCI.

Mobile ion-induced data retention failure in NOR flash memory cell

Data retention failures due to nonoptimized processes in NOR-type flash memory cells are presented. Contrary to the charge leakage through defective oxide dielectric surrounding the floating gate, the data loss observed depends on whether the bit line contact is close to the cell or not. It is found that the data loss exhibits a charge-state dependence during baking stresses as well as temperature dependence. Based on experimental results, sodium movement in sidewall spacers is established as an origin for the data retention failure in NOR-type flash memory cells. Employing a thin nitride overlayer results in a good data retention, supporting the hypothesis of sodium movement.

The challenges and limitations on triple level cell geometry and process beyond 20 nm NAND Flash technology

This paper investigates the challenges and difficulties of TLC cell geometry and process beyond 20nm NAND technology from the viewpoint of programmed Vth level, new HCI disturbance and charge loss in the highest programmed level.

Challenges and limitations of NAND flash memory devices based on floating gates

In this paper, the limitations and challenges of NAND flash memory devices based on floating gates are discussed. And, the newly adopted operation algorithms, such as intelligent incremental step pulse erase, various biasing in grouped W/Ls, virtual negative read and data randomization, and their results are exhibited.

The effect of hydrogen on program disturbance in sub-2ynm Nand flash

The Effect of hydrogen on program disturbance in sub-2ynm NAND flash is studied. It is supposed that boron atoms implanted for field stop are deactivated due to the formation of neutral boron-hydrogen pair. Boron deactivation results in the degradation of STI leakage and program disturbance. By adopting hydrogen reducing process, program disturbance of 2ynm NAND flash is successfully improved.

A Investigation of E/W Cycle Characteristics for 2y-nm MLC NAND Flash Memory Devices

In this paper, the challenges of NAND flash memory devices with E/W cycling characteristics are discussed. The large VTH shift in 2y-nm technology is investigated with various causes such as air-gap, poly2 valley plug gap-fill and string current. The countermeasures including process and operation algorithm are also exhibited to improve the reliability of 2y-nm NAND Flash memory device.

Data retention failure in NOR flash memory cells

We present the results of investigations into the causes of threshold voltage instabilities in NOR-type flash memory cells due to charge loss and charge gain. A large threshold voltage shift of several volts has been observed on specific cells, which have a bit line contact that is misaligned and touches the side wall spacer. This data retention failure is characterized by both a temperature dependence of charge loss, showing an activation energy of about 1.12 eV, and a dependence of the magnitude of charge gain on the charged state in previous retention bake stressing. Employing a thin silicon nitride layer between the side wall spacer and the bit line contact results in good data retention. Based on these results, sodium ion contamination is proposed as the origin of charge loss and charge gain in NOR-type flash cells fabricated using a non-optimized process.

Novel integration technologies for improving reliability in NAND flash memory

NAND flash has been scaled down intensively to 2Y nm generation to satisfy the increasing demand for high-density memories. However, as technology node advances, various scaling barriers newly appeared and reliability characteristics of NAND flash such as endurance and data retention deteriorated. Maximum Vth of a programmed cell becomes lower with scaling down, resulting in insufficient program window for MLC operation. Floating gate (FG) and inter-poly dielectric (IPD) structure must be carefully optimized to maximize saturated level of programmed Vth. The tight control of Vth distribution is one of the main issues in scaling for reliability margin. By decreasing depletion in floating gate and control gate (CG), widening of cell Vth distribution width can be efficiently suppressed. The effect of traps in gate oxide to reliability increases with the decrease in cell dimension. To lower interface trap of gate oxide, hydrogen reducing back-end-of line (BEOL) process is introduced. By using new BEOL process, endurance and data retention characteristics are drastically enhanced. In this paper, we will present the major scaling issues and integration technologies for improving reliability in NAND flash memory for 2Ynm generation and beyond.

RTS noise reduction of 1Y-nm floating gate NAND flash memory using process optimization

We report the random telegraph noise characteristics of 1Y-nm floating gate NAND Flash memory and behaviors of random telegraph noise generating traps. The location of selected traps are extracted and their behaviors in different temperature are also investigated. To reduce the threshold voltage fluctuations, we optimize the process conditions of 1Y-nm floating gate NAND Flash memories including tunnel oxide reduction and modification on annealing conditions. We successfully decrease the threshold voltage fluctuations as low as that of 2Y-nm floating gate NAND Flash memories.