Gi-Hyun Bae

Modeling of

A threshold-voltage (Vth) shift of sub-100-nm NAND flash-memory cell transistors was modeled systematically, and the modeling was verified by comparing with the data from measurement and 3-D device simulation. The Vth shift of the NAND flash-memory cell was investigated by changing parameters such as gate length, width, drain voltage, dielectric material between cells, space between cells, lightly doped-drain depth, and adjacent-cell bias. The proposed model covers two dominant device physics: capacitance coupling effect between adjacent cells and short-channel effect. Our model showed an accurate prediction of the Vth shift of NAND flash-memory array and a good agreement with the data from simulation and measurement.

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In this paper, the limitations and challenges of NAND flash memory devices based on floating gates are discussed. And, the newly adopted operation algorithms, such as intelligent incremental step pulse erase, various biasing in grouped W/Ls, virtual negative read and data randomization, and their results are exhibited.

Shift in nand Flash-Memory Cell Device Considering Crosstalk and Short-Channel Effects

In this study, physical properties of different trapping nitrides were extracted, and the program efficiency of MANOS cell was explained. We also showed shallow traps were generated at trapping nitride by etching damage, and this could be cured resulting great improvement of cell performance. Lastly, erasure mechanism of TiN-gate MANOS cell was discussed with some experimental and modeling results.

Challenges and limitations of NAND flash memory devices based on floating gates

The Effect of hydrogen on program disturbance in sub-2ynm NAND flash is studied. It is supposed that boron atoms implanted for field stop are deactivated due to the formation of neutral boron-hydrogen pair. Boron deactivation results in the degradation of STI leakage and program disturbance. By adopting hydrogen reducing process, program disturbance of 2ynm NAND flash is successfully improved.

Modeling and Characterization of Program / Erasure Speed and Retention of TiN-gate MANOS (Si-Oxide-SiNx-Al2O3-Metal Gate) Cells for NAND Flash Memory

In this paper, the challenges of NAND flash memory devices with E/W cycling characteristics are discussed. The large VTH shift in 2y-nm technology is investigated with various causes such as air-gap, poly2 valley plug gap-fill and string current. The countermeasures including process and operation algorithm are also exhibited to improve the reliability of 2y-nm NAND Flash memory device.

The effect of hydrogen on program disturbance in sub-2ynm Nand flash

Ramping amplitude multi-frequency charge pumping technique is proposed to analyze the nitride traps in silicon?oxide?nitride?oxide?silicon (SONOS) structure. Based on the method, the trap density and the capture cross section at each location in oxide?nitride?oxide (ONO) gate stack can be extracted separately. The trap parameters extracted from the suggested model show that the traps located at tunnel-oxide/nitride interface whose capture cross section is lowest. The cause of large trap density at tunnel-oxide/nitride interface may be due to Si?Si bonding formation as reported in previous works.

A Investigation of E/W Cycle Characteristics for 2y-nm MLC NAND Flash Memory Devices

We report the dependence of Si–SiO2 interface trap density after Fowler–Nordheim (F/N) stress on various capping materials between gate stacks and an inter layer dielectric (ILD) in a NAND Flash memory cell. The interface trap density was characterized by charge pumping method (CPM). When the capping layer is an oxide, the Nit after F/N stress is approximately 2×1011 cm-2, which is about 50% smaller than that with a nitride layer. We found that the oxide layer causes compressive stress whereas the nitride layer causes a relatively high tensile stress in the underlying substrate by measuring the warp change of the substrate. To correlate the interface state density and data retention characteristics, we measured Vt shift after high-temperature baking. When an oxide capping layer is used, the retention characteristics of memory devices are greatly improved compared to the nitride capping case. These results show a good correlation between the interface characteristics and mechanical stress behaviors.

New Charge Pumping Method for Characterization of Charge Trapping Layer in Oxide?Nitride?Oxide Structure

NAND flash has been scaled down intensively to 2Y nm generation to satisfy the increasing demand for high-density memories. However, as technology node advances, various scaling barriers newly appeared and reliability characteristics of NAND flash such as endurance and data retention deteriorated. Maximum Vth of a programmed cell becomes lower with scaling down, resulting in insufficient program window for MLC operation. Floating gate (FG) and inter-poly dielectric (IPD) structure must be carefully optimized to maximize saturated level of programmed Vth. The tight control of Vth distribution is one of the main issues in scaling for reliability margin. By decreasing depletion in floating gate and control gate (CG), widening of cell Vth distribution width can be efficiently suppressed. The effect of traps in gate oxide to reliability increases with the decrease in cell dimension. To lower interface trap of gate oxide, hydrogen reducing back-end-of line (BEOL) process is introduced. By using new BEOL process, endurance and data retention characteristics are drastically enhanced. In this paper, we will present the major scaling issues and integration technologies for improving reliability in NAND flash memory for 2Ynm generation and beyond.

Analysis of Si–SiO2 Interface Using Charge Pumping Method with Various Capping Materials between Gate Stacks and Inter Layer Dielectric in NAND Flash Memory

We have developed a 64Gb MLC NAND Flash using a sub-20 nm process technology, which realizes 800MB/s data transfer rate with DDR mode. In order to achieve 800MB/s transfer rate, we introduce slim transistors of ~3 nm-thick gate oxide and dual poly gate, in addition to conventional NAND Flash transistors. Furthermore, some new novel circuitry has been implemented, such as Split Power Page Buffer, Local Sense-Amplifier (LSA) Data In/Out Architecture, Regulated Widlar Reference Generator and Low VCC Row Decoder.

Novel integration technologies for improving reliability in NAND flash memory

We have characterized the low frequency noise (LFN) in the NAND flash memory string, for the first time, and shown its fundamental properties. As a result, the NAND flash memory shown specific LFN characteristics in conditions such as bit-line bias, word-line bias, read current and program or erase state of each cell in a string. Also the LFN was investigated with program/erase (P/E) cycling of a cell or all cells in a string, and shown several tens mV of maximum threshold voltage fluctuation after ~100 k cycling at 70 nm node. Lastly, we have predicted the effects of the LFN in sub-70 nm NAND flash memory.