Kunal Singh

Effects of fly ash additions on the mechanical and other properties of porcelainised stoneware tiles

The effect of fly ash additions on the mechanical properties of porcelainised stoneware tile composition has been investigated. Fly ash additions in the range of 0–40 wt% have been added in to the tile body composition, wet milled, spray dried, shaped and fired at 1250°C. The MOR strength improved with increasing fly ash content and reached maximum when 25–30 wt% fly ash used, and with greater additions it decreased. A linear correlation between strength development and mullite formation was found. The tiles with 25 wt% fly ash had improved bending strength, abrasion resistance and hardness compared to the conventional tiles and conform to all other properties at an EN standard specification.

2-D Analytical Modeling of Threshold Voltage for Graded-Channel Dual-Material Double-Gate MOSFETs

A 2-D analytical model for the surface potential and threshold voltage of graded-channel dual-material double-gate (GCDMDG) MOSFETs obtained by intermixing the concepts of graded doping in channel and dual material in gate engineering has been proposed. The parabolic approximation method has been explored for determining the potential distribution function of the device by solving Poissons equation with suitable boundary conditions. The threshold voltage roll-off, drain-induced barrier lowering and lateral electric field have also been examined. The effects of different device parameters on device performance have been evaluated to check its figure-of-merit over the graded-channel double-gate (GCDG) and dual-material double-gate (DMDG) structures. For validation of the proposed model, the results have been compared with the numerical simulation data obtained by ATLAS™, a 2-D device simulator from SILVACO.

A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors With a SiO 2 /High-

A compact 2-D analytical model for electrical characteristics such as surface potential, drain current, and threshold voltage of double-gate tunnel FET (DG TFETs) with a SiO2/High-k stacked gate-oxide structure is proposed in this paper. Poissons equation has been solved using parabolic approximation method to model the channel potential. The band-to-band tunneling generation rate has been expressed as a function of channel electric field derived from the channel potential and then integrated analytically over the channel thickness to derive the drain current of the stacked-gate DG TFETs using the shortest tunneling path (Ltmin) concept. The effect of source/drain depletion regions has been included for the better accuracy of the proposed model. The maximum transconductance method has finally been used to extract the threshold voltage from the drain current of the device. The effects of various device parameters on the channel potential, drain current, and threshold voltage have been investigated. The model results have been compared with the simulation data obtained using the commercially available ATLAS 2-D device simulator from SILVACO for the validity of the proposed model.

k

This paper proposes an analytical 2-D model for the channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile. The 2-D Poisson equation has been solved by using the evanescent-mode analysis to obtain the potential distribution function in the channel. The position of the conduction path also has been modeled to calculate the potential at different positions of the conduction path. The validity of the proposed 2-D potential and threshold voltage models is shown by comparing the results with the simulation data obtained by a 2-D TCAD ATLAS device simulator.

Stacked Gate-Oxide Structure

A physics-based 2-D analytical model for surface potential, electric field, drain current, subthreshold swing (SS) and threshold voltage of dual-material (DM) double-gate tunnel FETs (DG TFETs) with SiO2/HfO2 stacked gate-oxide structure has been developed in this paper. The parabolic-approximationtechnique, with suitable boundary conditions, has been used to solve Poisson’s equation in the channel region. Channel potential model is used to develop electric field expression. The drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the channel thickness. Threshold voltage has been extracted by maximum transconductance method. The proposed model also demonstrates that the proper choice of work function for both the latterly contacting gate electrode (near the source and drain) materials which can give better results in terms of input-output characteristics, SS, and

Analytical Modeling of Channel Potential and Threshold Voltage of Double-Gate Junctionless FETs With a Vertical Gaussian-Like Doping Profile

{I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}

2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO 2 /HfO 2 Stacked Gate-Oxide Structure

than the conventional TFET devices. Although the proposed model has been primarily developed for Si-channel-based DM DG TFET devices, however, the model has also been shown to be applicable for other materials like SiGe (indirect bandgap) and InAs channel-based TFET structures. The results of the proposed model have been validated against the TCAD simulation results obtained by using SILVACO ATLAS device simulation software.

2-D Analytical Threshold Voltage Model for Dielectric Pocket Double-Gate Junctionless FETs by Considering Source/Drain Depletion Effect

This paper proposes an analytical threshold voltage model for the dielectric pocket double gate (DP-DG) junctionless FETs (JLFETs). The channel potential function has been obtained by solving 2-D Poisson’s equation using an evanescent mode analysis with suitable boundary conditions. The potential function has then been used for modeling the threshold voltage to investigate the effects of the DP thickness and length on the short-channel effects of the structure. The effects of source and drain depletion regions have been included for improving the accuracy of the model. The model results of DP-DG JLFETs have been compared with the simulation data obtained from the 2-D TCAD ATLAS device simulator.

Analytical Modeling of Potential Distribution and Threshold Voltage of Gate Underlap DG MOSFETs with a Source/Drain Lateral Gaussian Doping Profile

This paper reports a new two-dimensional (2D) analytical model for the potential distribution and threshold voltage of the short-channel symmetric gate underlap ultrathin DG MOSFETs with a lateral Gaussian doping profile in the source (S)/drain (D) region. The parabolic approximation and conformal mapping techniques have been explored for solving the 2D Poisson’s equation to obtain the channel potential function of the device. The effects of straggle parameter (of the lateral Gaussian doping profile in the S/D region), underlap length, gate length, channel thickness and oxide thickness on the surface potential and threshold voltage have been investigated. The loss of switching speed due to the drain-induced barrier lowering (DIBL) has also been reported. The proposed model results have been validated by comparing them with their corresponding TCAD simulation data obtained by using the commercially available 2D ATLAS™ simulation software.

Strain-Induced Plasma Radiation in Terahertz Domain in Strained-Si-on-Insulator MOSFETs

This paper reports an ATLAS-based simulation study for investigating the strain-induced current instability in terms of negative differential resistance in strained-Si-on-insulator (SSOI) MOSFETs for terahertz (THz) emission. The variations of output drain current-voltage characteristics of the devices have been studied by varying the device parameters such as the gate length and strain in the channel. The effects of these parameters on the resonance plasma frequency have also been investigated. The large signal transient simulation of the device has been explored for generating a 4-THz sinusoidal signal using the SSOI MOSFETs. Prediction of this study may work as a stepping stone toward the development of solid-state microwave sources in the terahertz domain using the well-matured CMOS technology.