Mirgender Kumar

Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor

In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.

Investigation of the novel attributes of a fully depleted dual-material gate SOI MOSFET

The novel features of a fully depleted (FD) dual-material gate (DMG) silicon-on-insulator (SOI) MOSFET are explored theoretically and compared with those of a compatible SOI MOSFET. The two-dimensional numerical simulation studies demonstrate the novel features as threshold voltage roll-up and simultaneous transconductance enhancement and suppression of short-channel effects offered by the FD DMG SOI MOSFET. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate material. This work illustrates the benefits of high-performance FD DMG SOI MOS devices over their single material gate counterparts and provides an incentive for further experimental exploration.

Bipolar Charge-Plasma Transistor: A Novel Three Terminal Device

A distinctive approach for forming a lateral bipolar charge-plasma transistor (BCPT) is explored using 2-D simulations. Different metal work-function electrodes are used to induce n- and p-type charge-plasma layers on undoped silicon-on-insulator (SOI) to form the emitter, base, and collector regions of a lateral n-p-n transistor. Electrical characteristics of the proposed device are simulated and compared with that of a conventionally doped lateral bipolar junction transistor (BJT) with identical dimensions. Our simulation results demonstrate that the BCPT concept will help us realize a superior bipolar transistor in terms of a high current gain, as compared with a conventional BJT. This BCPT concept is suitable in overcoming doping issues such as dopant activation and high-thermal budgets, which are serious issues in ultrathin SOI structures.

New dual-material SG nanoscale MOSFET: analytical threshold-voltage model

A new analytical model for the surface potential and threshold voltage of a surrounding-gate MOSFET with dual-material gate is presented to investigate the short-channel effects. The model results accurately predict the threshold-voltage roll off for channel lengths even less than 90nm. The accuracy of the model results is verified using two-dimensional simulation.

Compact Analytical Threshold-Voltage Model of Nanoscale Fully Depleted Strained-Si on Silicon–Germanium-on-Insu lator (SGOI) MOSFETs

In this paper, a physically based analytical threshold-voltage model is developed for nanoscale strained-Si on silicon-germanium-on-insulator MOSFETs for the first time, taking into account short-channel effects. The model is derived by solving the 2-D Poisson equation in strained-Si and SiGe layers. The effects of various important device parameters like strain (Ge mole fraction in the SiGe layer), body doping, gate workfunction, strained-Si thin film and SiGe layer thickness, etc., has been considered. We have demonstrated that increasing strain in order to enhance device performance can lead to undesirable threshold-voltage rolloff. The model is found to agree well with the 2-D simulation results

A simple analytical threshold voltage model of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs

For the first time, a simple and accurate analytical model for the threshold voltage of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs is developed by solving the two-dimensional (2-D) Poisson equation. In the proposed model, the authors have considered several important parameters: 1) the effect of strain (in terms of equivalent Ge mole fraction); 2) short-channel effects; 3) strained-silicon thin-film doping; 4) strained-silicon thin-film thickness; and 5) gate work function and other device parameters. The accuracy of the proposed analytical model is verified by comparing the model results with the 2-D device simulations. It has been demonstrated that the proposed model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, i.e., with increasing equivalent Ge concentration. The proposed compact model can be easily implemented in a circuit simulator

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors analytical model is verified using two-dimensional device simulations.

Leakage current reduction techniques in poly-Si TFTs for active matrix liquid crystal displays: a comprehensive study

This paper critically examines the leakage current reduction techniques for improving the performance of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) used in active matrix liquid crystal displays. This is a first comprehensive study in literature on this topic. The review assesses important proposals to circumvent the leakage current problem in poly-Si TFTs and a short evaluation of strengths and weaknesses specific to each method is presented. Also, a new device structure called the triple-gate poly-Si TFT (TG-TFT) is discussed. The key idea in the operation of this device is to make the dominant conduction mechanism in the channel to be controlled by the accumulation charge density modulation by the gate and not by the gate-induced grain barrier lowering. Using two-dimensional and two-carrier device simulation, it is demonstrated that the TG-TFT exhibits a significantly diminished pseudosubthreshold conduction leading to several orders of magnitude reduction in the OFF-state leakage current when compared with a conventional poly-Si TFT. The reasons for the improved performance are explained

Impact of Strain or Ge Content on the Threshold Voltage of Nanoscale Strained-Si/SiGe Bulk MOSFETs

The impact of strain on the threshold voltage of nanoscale strained-Si/SiGe MOSFETs is studied by developing a compact analytical model. Our model includes the effects of strain (Ge mole fraction in SiGe substrate), short-channel length, source/drain junction depths, substrate (body) doping, strained silicon thin-film thickness, gate work function, and other device parameters. The model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, i.e., with increasing Ge concentration in SiGe substrate. The accuracy of the results obtained using our analytical model is verified using two-dimensional device simulations.

Dual-Material-Gate Technique for Enhanced Transconductance and Breakdown Voltage of Trench Power MOSFETs

In this brief, we propose a new dual-material-gate-trench power MOSFET that exhibits a significant improvement in its transconductance and breakdown voltage without any degradation in on-resistance. In the proposed structure, we have split the gate of a conventional trench MOSFET structure into two parts for work-function engineering. The two gates share the control of the inversion charge in the channel. By using 2-D numerical simulation, we have shown that by adjusting the lengths of the two gates to allow equal share of the inversion charge by them, we get the optimum device performance. By using N+ poly-Si as a lower gate material and P+ poly-Si as an upper gate material, approximately 44% improvement in peak transconductance and 20% improvement in breakdown voltage may be achieved in the new device compared to the conventional trench MOSFET.