Kunhyuk Kang

Impact of NBTI on the temporal performance degradation of digital circuits

Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict the delay degradation of a wide class of digital logic gate based on both worst case and activity dependent threshold voltage change under NBTI. We show that by knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We find that digital circuits are much less sensitive (approximately 9.2% performance degradation in ten years for 70 nm technology) to NBTI degradation than previously anticipated.

Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis

One of the major reliability concerns in nanoscale very large-scale integration design is the time-dependent negative- bias-temperature-instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (Vt) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, focusing on the conventional 6T-SRAM-array topology. An analytical expression for the time-dependent Vt degradation in PMOS transistors based on the empirical reaction-diffusion (RD) framework was employed for our analysis. Using the RD-based Vt model, we analytically examine the impact of NBTI degradation in critical performance parameters of SRAM array. These parameters include the following: (1) static noise margin; (2) statistical READ and WRITE stability; (3) parametric yield; and (4) standby leakage current (IDDQ). We show that due to NBTI, READ stability of SRAM cell degrades, while write stability and standby leakage improve with time. Furthermore, by carefully examining the degradation in leakage current due to NBTI, it is possible to characterize and predict the lifetime behavior of NBTI degradation in real circuit operation.

Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits

Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm taking NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area one can ensure reliable performance of circuits for 10 years

Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance

Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability concerns in sub-100 nm technologies. So far, studies of NBTI and its impact on circuit performance have assumed an average behavior of the degradation process. However, in very short channel devices, finite number of Si-H bonds in the channel can induce a statistical random variation of the degradation process. This results in significant random Vt variations in PMOS transistor. The NBTI induced variation depends on operating temperature and the effective stress period for the specific device. In this paper, we analyze the impact of stochastic temporal NBTI variations and propose a compact circuit level Vt model. Using the proposed model, we show how temporal Vt variations can affect the lifetime performance of different circuit topologies including 6T SRAM cell and random combinational logic circuits.

NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?

This paper evaluates the severity of negative bias temperature instability (NBTI) degradation in two major circuit applications: random logic and memory array. For improved lifetime stability, we propose/select an efficient reliability-aware circuit design methodologies. Simulation results obtained from 65nm PTM node shows that NBTI induced degradation in random logic is considerably lower than that of a single transistor. As a result, simple delay guard-banding can efficiently mitigate the impact of NBTI in random logic. On the other hand, NBTI degradation in memory shows much severe effect especially when combined with the impact of random process variation, NBTI can dramatically reduce the READ stability of memory cells. Hence, aggressive design techniques such as stand-by VDD scaling or adaptive body biasing (ABB) are required in memory application to minimize the impact of NBTI.

Statistical Timing Analysis using Levelized Covariance Propagation

Variability in process parameters is making accurate timing analysis of nanoscale integrated circuits an extremely challenging task. In this paper, we propose a new algorithm for statistical timing analysis using levelized covariance propagation (LCP). The algorithm simultaneously considers the impact of random placement of dopants (which makes every transistor in a die independent in terms of threshold voltage) and the spatial correlation of the process parameters such as channel length, transistor width and oxide thickness due to the intra-die variations. It also considers the signal correlation due to reconvergent paths in the circuit. Results on several benchmark circuits in 70 nm technology show an average of 0.21 % and 1.07 % errors in mean and the standard deviation, respectively, in timing analysis using the proposed technique compared to the Monte-Carlo analysis.

Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits

Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold-voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm, taking the NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area, one can ensure a reliable performance of circuits for ten years

Reliability Implications of Bias-Temperature Instability in Digital ICs

Bias temperature instability (BTI) is one of the major reliability challenges in nanoscale CMOS technology. This article investigates the severity of such degradation in logic and memory circuits. The simulation results reveal that BTI poses severe constraints on reliable memory design, especially in the presence of random process variations.

On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures

Performance variability in digital integrated circuits can largely affect parametric yield and product reliability in ultra deep submicrometer technologies. As a result, variation resilience is becoming an essential design requirement for future technology nodes, especially for timing critical applications. This paper proposes an on-chip variability sensor using phase-locked loop (PLL) to detect process, supply voltage (V DD), and temperature variations (process, voltage, and temperature variation) or even temporal reliability degradation stemming from negative bias temperature instability. Our analysis shows that control voltage (V cnt) of voltage-controlled oscillator in PLL can be used as a dynamic performance signature of an operating IC. Along with the proposed PLL-based sensor circuit, we also propose a variation-resilient system technique using adaptive body biasing (ABB). The PLL V cnt signal is efficiently transformed to an optimal body bias signal for various circuit blocks to avoid possible timing failures. Correspondingly, circuits can be designed with significantly relaxed timing constraint compared to conventional approaches, where a large amount of design resources can be wasted to take care of the worst-case situations. We demonstrated our approach on a test chip fabricated in IBM 130-nm CMOS technology. Measurement results show that the PLL-based sensor is cable of tracking various sources of circuit variations. Optimization analysis shows that 42% and 43% reduction in area and power can be obtained using our approach compared to the worst-case sizing. The proposed study refers to our previous study introduced in with major improvements in measurement results and analysis.

Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring

The inter-die and intra-die variations in process parameters result in large number of failures in an SRAM array degrading the design yield. In this paper, we propose an adaptive repairing technique for SRAM based on leakage and delay monitoring. Leakage and delay monitoring is used to effectively separate dies with different inter-die Vts from each other. Using the leakage (or delay) monitoring and adaptive body bias, we propose a reliable and self-repairing SRAM which has reduced number of parametric failures under high inter-die and intra-die Vt variations. The proposed self-repairing SRAM improves the design yield by 5%-40% in predictive 70nm technology from BPTM