Haldun Kufluoglu

Impact of NBTI on the temporal performance degradation of digital circuits

Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict the delay degradation of a wide class of digital logic gate based on both worst case and activity dependent threshold voltage change under NBTI. We show that by knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We find that digital circuits are much less sensitive (approximately 9.2% performance degradation in ten years for 70 nm technology) to NBTI degradation than previously anticipated.

A comprehensive model for PMOS NBTI degradation : Recent progress

Abstract Negative bias temperature instability (NBTI) is a well-known reliability concern for PMOS transistors. We review the literature to find seven key experimental features of NBTI degradation. These features appear mutually inconsistent and have often defied easy interpretation. By reformulating the Reaction–Diffusion model in a particularly simple form, we show that these seven apparently contradictory features of NBTI actually reflect different facets of the same underlying physical mechanism.

Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation

Recent advances in experimental techniques (on-the- fly and ultrafast techniques) allow measurement of threshold voltage degradation due to negative-bias temperature instability (NBTI) over many decades in timescale. Such measurements over wider temperature range (-25degC to 145degC), film thicknesses (1.2-2.2 nm of effective oxide thickness), and processing conditions (variation of nitrogen within gate dielectric) provide an excellent framework for a theoretical analysis of NBTI degradation. In this paper, we analyze these experiments to refine the existing theory of NBTI to 1) explore the mechanics of time transients of NBTI over many orders of magnitude in time; 2) establish field dependence of interface trap generation to resolve questions regarding the appropriateness of power law versus exponential projection of lifetimes; 3) ascertain the relative contributions to NBTI from interface traps versus hole trapping as a function of processing conditions; and 4) briefly discuss relaxation dynamics for fast-transient NBTI recovery that involves interface traps and trapped holes.

Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis

One of the major reliability concerns in nanoscale very large-scale integration design is the time-dependent negative- bias-temperature-instability (NBTI) degradation. Due to the higher operating temperature and increasing vertical oxide field, threshold voltage (Vt) of PMOS transistors can increase with time under NBTI. In this paper, we examine the impact of NBTI degradation in memory elements of digital circuits, focusing on the conventional 6T-SRAM-array topology. An analytical expression for the time-dependent Vt degradation in PMOS transistors based on the empirical reaction-diffusion (RD) framework was employed for our analysis. Using the RD-based Vt model, we analytically examine the impact of NBTI degradation in critical performance parameters of SRAM array. These parameters include the following: (1) static noise margin; (2) statistical READ and WRITE stability; (3) parametric yield; and (4) standby leakage current (IDDQ). We show that due to NBTI, READ stability of SRAM cell degrades, while write stability and standby leakage improve with time. Furthermore, by carefully examining the degradation in leakage current due to NBTI, it is possible to characterize and predict the lifetime behavior of NBTI degradation in real circuit operation.

Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits

Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm taking NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area one can ensure reliable performance of circuits for 10 years

Theory of interface-trap-induced NBTI degradation for reduced cross section MOSFETs

Negative Bias Temperature Instability (NBTI)-induced degradation for ultra-scaled and future-generation MOSFETs is investigated. Numerical simulations based on Reaction-Diffusion framework are implemented. Geometric dependence of degradation arising from the transistor structure and scaling is incorporated into the model. The simulations are applied to narrow-width planar triple-gate and surround-gate MOSFET geometries to estimate the NBTI reliability under several scaling scenarios. Unless the operating voltages are optimized for specific geometry of transistor cross section, the results imply worsened NBTI reliability for the future-generation devices based on the geometric interpretation of the NBTI degradation. A time-efficient and straightforward analysis is developed to predict the degradation. This compact model confirms the numerical simulations.

A Generalized Reaction–Diffusion Model With Explicit H–

In this paper, negative-bias temperature-instability (NBTI) modeling, based on a generalized reaction-diffusion framework, is presented. Unlike the previous models, the release of atomic hydrogen from the Si-H bonds at the Si/oxide interface and its subsequent conversion into molecular H2 are considered without the (unphysical) assumption of instantaneous transition. The conversion reactions are handled explicitly with finite transition time and numerical solutions that contain both H and H 2 dynamics are obtained. The conversion reactions result in a distinct time behavior which cannot be predicted from either H- or H2-only simulations. The results are then explained analytically. The implications of hydrogen conversion dynamics on saturation of NBTI characteristics and device lifetimes are also discussed

\hbox{H}_{2}

A unification of time-exponents for negative bias temperature instability (NBTI) and hot carrier injection (HCI) is established under the geometric interpretation of interface trap generation. Resolving the fundamental inconsistencies, a numerical reaction-diffusion (R-D) model that agrees with recent measurements is developed. The implications regarding the degradations of future sub-100 nm planar and surround-gate MOSFETs are presented.

Dynamics for Negative-Bias Temperature-Instability (NBTI) Degradation

Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold-voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm, taking the NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area, one can ensure a reliable performance of circuits for ten years

A geometrical unification of the theories of NBTI and HCI time-exponents and its implications for ultra-scaled planar and surround-gate MOSFETs

Off-state degradation in drain-extended NMOS transistors is studied. Carefully designed experiments and well-calibrated simulations show that hot carriers, which are generated by impact ionization of surface band-to-band tunneling current, are responsible for interface damage during off-state stress. Classical on-state hot carrier degradation has historically been associated with broken equivSi-H bonds at the interface. In contrast, the off-state degradation in drain-extended devices is shown to be due to broken equivSi-O- bonds. The resultant degradation is universal, which enables a long-term extrapolation of device degradation at operating bias conditions based on short-term stress data. Time evolution of degradation due to broken equivSi-O- bonds and the resultant universal behavior is explained by a bond-dispersion model. Finally, we show that, under off-state stress conditions, the interface damage that is measured by charge-pumping technique is correlated with dielectric breakdown time, as both of them are driven by broken equivSi-O- bonds.