Keejong Kim

A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM

We propose a novel Schmitt trigger (ST) based differential 10-transistor SRAM (static random access memory) bitcell suitable for subthreshold operation. The proposed Schmitt trigger based bitcell achieves 1.56 x higher read static noise margin (SNM) ( Vdd = 400 mV) compared to the conventional 6T cell. The robust Schmitt trigger based memory cell exhibits built-in process variation tolerance that gives tight SNM distribution across the process corners. It utilizes differential operation and hence does not require any architectural changes from the present 6T architecture. At iso-area and iso-read-failure probability the proposed memory bitcell operates at a lower (175 mV) Vdd with 18% reduction in leakage and 50% reduction in read/write power compared to the conventional 6T cell. Simulation results show that the proposed memory bitcell retains data at a supply voltage of 150 mV. Functional SRAM with the proposed memory bitcell is demonstrated at 160 mV in 0.13 mum CMOS technology.

A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM

We propose a novel Schmitt Trigger (ST) based fully differential 10 transistor SRAM (Static Random Access Memory) bitcell suitable for sub-threshold operation. The proposed Schmitt trigger based bitcell achieves 1.56X higher read static noise margin (SNM) (VDD = 400mV) compared to the conventional 6T cell. The robust Schmitt trigger based memory cell exhibits built in process variation tolerance that gives tight SNM distribution across the process corners. It utilizes fully differential operation and hence does not require any architectural changes from the present 6T architecture. At iso-area and iso-read-failure probability the proposed memory bitcell operates at a lower (175mV) VDD with 18% reduction in leakage and 50% reduction in read/write power compared to the conventional 6T cell. Simulation results show that the proposed memory bitcell retains data at a supply voltage of 150mV. Functional SRAM with the proposed memory bitcell is demonstrated at 160mV in 0.13μm CMOS technology.

Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS

In nanoscaled technologies, increased inter-die and intra-die variations in process parameters can result in large number of parametric failures in an SRAM array, thereby, degrading yield. In this paper, we propose a self-repairing SRAM to reduce parametric failures in memory. In the proposed technique, on-chip monitoring of leakage current and/or delay of a ring oscillator is used to determine the inter-die process corner of an SRAM die. Depending on the inter-die Vt shift, the self-repair system selects the proper body bias to reduce parametric failures. Simulations using predictive 70-nm device show that the proposed self-repairing SRAM improves design yield by 5%-40%. A test-chip is designed and fabricated in IBM 0.13-mum CMOS technology to successfully demonstrate the operation of the self-repair system.

A Low-Power SRAM Using Bit-Line Charge-Recycling

We propose a new low-power SRAM using bit-line Charge Recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtained by recycled charge from its adjacent bit-line capacitance. In order to improve the data retention capability of un-selected cells during write, the power supply lines of memory cells in one column are connected to each other and separated from the power lines of other columns. A test-chip is fabricated in 0.13μm CMOS and measurement results show 88% reduction in total power compared to the conventional SRAM (CON-SRAM) at VDD=1.5V and f=100MHz.

Process variation tolerant SRAM array for ultra low voltage applications

In this work, we propose a Schmitt Trigger (ST) based differential sensing SRAM bitcell that can operate at ultra-low supply voltage. The proposed Schmitt Trigger SRAM cell addresses the fundamental conflicting design requirement of read versus write operation of a conventional 6T cell. Schmitt Trigger operation gives better read-stability and as well as better write- ability compared to the standard 6T cell. The proposed ST bitcell incorporates a built-in feedback mechanism, achieving process variation tolerance -- a must for future nano-scaled technology nodes. Measurements on 10 test-chips fabricated in 130 nm technology show that the proposed Schmitt Trigger bitcell gives 58% higher read Static Noise Margin (SNM), 2X higher write- trip-point and 120 mV lower read Vmin compared to the conventional 6T cell. The ST SRAM array is operational at 150mV of supply voltage.

Characterization and estimation of circuit reliability degradation under NBTI using on-line I DDQ measurement

Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characterize and estimate the lifetime circuit reliability under NBTI degradation. Unlike conventional approaches, where a representative fMAX (maximum operating frequency) measurement from timing critical circuitry is used, we propose to utilize the standby circuit leakage IDDQ as a metric to detect and characterize temporal NBTI degradation in digital circuits. Compared to the fMAX based approach, the proposed IDDQ based technique benefits from lower test cost and improved capability of estimating reliability of complex circuitries such as ALUs and SRAM arrays. We have derived an analytical expression for circuit IDDQ from the analytical PMOS Vt degradation model (DeltaVt prop t1/6 ). The proposed model is verified with measurement data obtained from a test chip fabricated in 130 nm technology. Furthermore, we examine the possible applications of our proposed IDDQ based NBTI characterization. We show that the temporal degradation in static noise margin (SNM) of SRAM array and fMAX of random logic circuits are highly correlated to the IDDQ measurement, and this relationship can be used to predict long term circuit reliability.

A 85mV 40nW Process-Tolerant Subthreshold 8×8 FIR Filter in 130nm Technology

Subthreshold operation is limited by low performance and high susceptibility to process variation. We propose variation tolerant ultra-dynamic voltage scaling (UDVS), and as an example we present an 8 times 8 process-tolerant FIR filter, working in both superthreshold and subthreshold regions featuring adaptive beta-ratio modulation and integrated level converters. Measurements show that the filter works at 85 mV consuming 40 nW, and the proposed method can salvage circuits which potentially failed to operate due to variations.

FinFET Based SRAM Design for Low Standby Power Applications

It is well known that leakage savings using transistor stacks is not effective in double-gate technologies such as FinFETs (back and front-gate connected together), due to the absence of body effect. However, transistor stacking along with independent gate operation of FinFETs can offer larger leakage savings compared to that of bulk devices. In this paper, we show that the sleep transistor based source biasing technique can be an effective means to control leakage for static random access memory (SRAM) with independent gate FinFETs. The array area penalty of the approach is ~5%. We show that lower gate leakage at a given short channel effect (SCE), lower band-to-band tunneling and higher sub-threshold slope offered by well tempered undoped ultra thin body FinFETs can lead to ultra low power SRAM arrays

Variation resilient low-power circuit design methodology using on-chip phase locked loop

This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize on-chip phase locked loop (PLL) as a sensor to detect process, VDD, and temperature (PVT) variations or even temporal degradation stemming from negative bias temperature instability (NBTI). We will show that control voltage (Vcnt) of voltage controlled oscillator (VCO) in PLL can dynamically capture performance variations in circuit. By utilizing the Vcnt signal of PLL, we propose variation resilient circuit design using adaptive body bias (VR-ABB). Vcnt is used to generate an optimal body bias for various circuit blocks in order to avoid possible timing failures. Correspondingly, circuits can be designed with a significantly relaxed timing constraint compared to the conventional approaches, where a large amount of design resources can be wasted to take care of the worst case situations. We have demonstrated our approach using an 8 bit ripple carry adder (RCA) as an example circuit. Results show that even under extreme variations, reasonable parametric yield can be maintained while minimizing other design resources such as area and power.

Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM

Increasing source voltage (source-biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source voltage can significantly increase data flipping in standby mode (hold failures) resulting in faulty memories. This imposes serious concerns in reducing standby power with source-bias. In this paper, we analyze the effect of source bias on hold failures under both inter-die and intra-die variations. We propose a self-calibrating SRAM for aggressively reducing leakage while maintaining the hold failures under control