Kuo-Liang Lu

Planarization wrinkle in CIS color filter process

The mechanism of planarization wrinkle defect in complementary metal oxide semiconductor (CMOS) color filter process is discussed in this paper. The wrinkle phenomena occurred as the planarization resist thickness decreased and became worse after high temperature baking was implemented. In experiment, the effect of factors on the wrinkle with KLA scanning such as resist thickness, soft bake temperature and time after resist coating and development puddle time were analyzed. From the data, the wrinkle is connectable with the developer penetration into and break through the resist film. Some solutions can be applied to solve this problem. Strengthening the resist film by increasing expose energy to get higher degree of polymerization is the best solution. Increasing resist thickness also can inhibit wrinkle but it is limited by the overall stack height for optimizing microlens focal length. Prolonging the soft bake time and reducing the puddle time of development to eliminate the penetration effect of developer are not obvious.

New novel method for solving ASML alignment fail (model error) in color filter process

For better resolution and throughput concern on color filter process, we use ASML5500/100 for color filter production instead of 1X CANON, but it often suffered alignment fail (error code: model error) at the green layer. Some items have been studied: (1) pattern close to ASML PM mark; (2) level sensor issue (level sensor contamination, plate tilt, level lens contamination); (3) different process sequence; (4) open the clear-out window at passivation layer to reduce interference effect. All of these items are proved no obviously influence to induce model error. By checking the spectrum of the green photo-resist, we found that it is low transmittance at 633 nm1 (the wavelength that the ASML alignment laser uses). Raising the transmittance by reducing the thickness of green resist is proved useful to eliminate the occurrence of model error. On the other hand, the ATHENATM provided by ASML which use red and green lights for alignment will get rid of the alignment failure.

Probe microloading effect of in-situ etch in EPROM stack gate process

An unpredictable significant microloading effect occurs between array and low photoresist ratio area when C2F6Cl2 and HBr are used as etch gas to define EPROM stack gate. Although we have examined etch time for array is enough, much poly residue still exist on those test keys with low photoresist ratio areas that lead to failure of electric parameter. On array area, polymer formed from C2F6 reactant gas trends to accumulate upon side-wall. Oppositely on the low photoresist area, there is almost not nay side-wall that can offer the medium absorbed by polymer. It will fall down and deposits upon poly surface. That will be a barrier. In the beginning, sufficient etch time often result from under- etch issue. We have modified etch time to get best optimal condition. Now, this issue does not occur any more.